公开(公告)号：US20150155323A1

公开(公告)日：2015-06-04

申请号：US14399735

申请日：2012-05-10

Applicant: SiliconFile Technologies Inc.

Inventor： Heui Gyun Ahn ,  Jun Ho Won

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14616 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present invention relates to a chip-stacked image sensor and to a method for manufacturing the same. More particularly, the present invention relates to a chip-stacked image sensor having a heterogeneous junction structure and to a method for manufacturing the same, in which a first semiconductor chip and a second semiconductor chip are manufactured using substrate materials suitable for the characteristics of sensors formed on each semiconductor substrate, and the semiconductor chips are stacked to form an image sensor. According to the chip-stacked image sensor having a heterogeneous junction structure and the method for manufacturing the same, the material for a first semiconductor substrate used in a first semiconductor chip and the material for a second semiconductor substrate used in a second semiconductor chip are different from each other, thus enabling characteristics of sensors formed on each semiconductor chip to be properly exhibited.

Abstract translation: 芯片堆叠式图像传感器及其制造方法技术领域本发明涉及芯片堆叠式图像传感器及其制造方法。 更具体地，本发明涉及具有异质结结构的芯片堆叠图像传感器及其制造方法，其中使用适合于传感器特性的基板材料制造第一半导体芯片和第二半导体芯片 形成在每个半导体衬底上，并且半导体芯片被堆叠以形成图像传感器。 根据具有异质结结构的芯片堆叠图像传感器及其制造方法，用于第一半导体芯片的第一半导体衬底的材料和用于第二半导体芯片中的第二半导体衬底的材料是不同的 从而能够适当地显示形成在各半导体芯片上的传感器的特性。

公开(公告)号：US09484377B2

公开(公告)日：2016-11-01

申请号：US14649710

申请日：2013-11-15

Applicant: SiliconFile Technologies Inc.

Inventor： Jun Ho Won ,  Won Ho Lee ,  Do Young Lee

IPC: H01L27/146 ,  H04N9/04

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14649 ,  H01L27/14685 ,  H01L27/14689 ,  H04N9/045

Abstract: The present invention relates to a CMOS image sensor including an infrared pixel with enhanced spectral characteristics in which a stepped portion is formed between color filters of RGB pixels and a filter of an infrared pixel, and a manufacturing method thereof. A stepped portion is formed between color filters and an infrared filter according to respective pixels and the thicknesses of the filters are arbitrarily adjusted regardless of the characteristics of material in the formation of the color filters and the infrared filter, so that crosstalk characteristics are improved.

Abstract translation: 本发明涉及一种CMOS图像传感器及其制造方法，该CMOS图像传感器包括具有增强的光谱特性的红外像素及其制造方法，其中在RGB像素的滤色器和红外像素的滤色器之间形成台阶部分。 根据各个像素，在滤色器和红外滤光器之间形成阶梯部分，并且无论滤色器和红外滤光器的形成中的材料的特性如何，都可任意调节滤光片的厚度，从而提高串扰特性。

公开(公告)号：US20150115330A1

公开(公告)日：2015-04-30

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。

公开(公告)号：US09553120B2

公开(公告)日：2017-01-24

申请号：US14529783

申请日：2014-10-31

Applicant: SiliconFile Technologies Inc.

Inventor： Jae Young Park ,  Young Ha Lee ,  Jun Ho Won ,  Do Young Lee

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.

Abstract translation: 这种技术能够简化工艺并且在使用背面照明光电二极管接合两个晶片以制造图像传感器时确保不对准裕度。 当通过3D CIS（CMOS图像传感器）制造工艺制造图像传感器时，使用一个晶片的通孔和另一个晶片的焊盘来电连接两个晶片，即第一晶片和第二晶片。 此外，当通过3D CIS制造工艺制造图像传感器时，两个晶片使用两个晶片的通孔电连接。