公开(公告)号：US20170325330A1

公开(公告)日：2017-11-09

申请号：US15176130

申请日：2016-06-07

Applicant: Subtron Technology Co., Ltd.

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Ching-Ta Chen ,  Mei-Chin Chang

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: A manufacturing method of a circuit substrate includes the following steps. A core layer having a core dielectric layer, a first patterned circuit layer and a second patterned circuit layer is provided. An electroless plating nickel layer is formed on the first patterned circuit layer and the second patterned circuit layer. The electroless plating nickel layer has a first thickness, and the first thickness is between 1 micrometer and 10 micrometers. A reducing process is performed on the electroless plating nickel layer so that the electroless plating nickel layer is thinned from the first thickness to a second thickness to form a thinned electroless plating nickel layer. The second thickness is between 0.01 micrometers and 0.9 micrometers. An electroless plating palladium layer is formed on the thinned electroless plating nickel layer. A surface metal passivation layer is formed on the electroless plating palladium layer.

公开(公告)号：US09591753B2

公开(公告)日：2017-03-07

申请号：US14849614

申请日：2015-09-10

Applicant: Subtron Technology Co., Ltd.

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Mei-Chin Chang ,  Ching-Ta Chen

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/18

CPC classification number: H05K1/09 ,  H05K1/111 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/072

Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。

公开(公告)号：US20160282055A1

公开(公告)日：2016-09-29

申请号：US15181434

申请日：2016-06-14

Applicant: Subtron Technology Co., Ltd.

Inventor： Ching-Sheng Chen

IPC: F28D15/04

CPC classification number: F28D15/046 ,  F28F21/04 ,  H01L23/3735 ,  H01L23/427 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/00014

Abstract: A heat dissipation plate including a heat-conductive material layer, a first metal layer, a metal substrate, a metal ring frame, and a second metal layer is provided. The heat-conductive material layer has an upper surface and a lower surface opposite to each other. The first metal layer is disposed on the lower surface of the heat-conductive material layer and has a first rough surface structure. The metal substrate is disposed below the first metal layer and has a second rough surface structure. The metal ring frame is disposed between the first metal layer and the metal substrate. The second metal layer is disposed on the upper surface of the heat-conductive material layer. The first and second rough surface structures and the metal ring frame define a fluid chamber, and a working fluid flows in the fluid chamber. A package structure including the heat dissipation plate is also provided.

Abstract translation: 提供了包括导热材料层，第一金属层，金属基板，金属环框架和第二金属层的散热板。 导热材料层具有彼此相对的上表面和下表面。 第一金属层设置在导热材料层的下表面上并且具有第一粗糙表面结构。 金属基板设置在第一金属层下方并具有第二粗糙表面结构。 金属环框架设置在第一金属层和金属基板之间。 第二金属层设置在导热材料层的上表面上。 第一和第二粗糙表面结构和金属环框架限定流体室，并且工作流体在流体室中流动。 还提供了包括散热板的封装结构。

公开(公告)号：US20160095256A1

公开(公告)日：2016-03-31

申请号：US14670434

申请日：2015-03-27

Applicant: Subtron Technology Co., Ltd.

Inventor： Ching-Sheng Chen

IPC: H05K7/20 ,  F28D15/02

CPC classification number: H01L23/427 ,  F28D15/04

Abstract: A heat dissipation module includes a hollow housing, a plurality of heat dissipation fins and heat dissipation liquid. The hollow housing includes a chamber, a side surface, a top surface and a bottom surface opposite to the top surface. The side surface is connected to the top surface and the bottom surface. The heat dissipation fins are disposed on the side surface. The heat dissipation liquid is contained within the chamber, and a specific heat of the heat dissipation liquid is substantially greater than or equal to 1 cal/g° C.

Abstract translation: 散热模块包括中空壳体，多个散热翅片和散热液体。 中空壳体包括腔室，侧表面，顶表面和与顶表面相对的底表面。 侧表面连接到顶表面和底表面。 散热片设置在侧面。 散热液体包含在室内，散热液的比热大致大于或等于1cal / g℃。

公开(公告)号：US20170013710A1

公开(公告)日：2017-01-12

申请号：US14849614

申请日：2015-09-10

Applicant: Subtron Technology Co., Ltd.

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Mei-Chin Chang ,  Ching-Ta Chen

IPC: H05K1/09 ,  H05K3/18 ,  H05K1/11

CPC classification number: H05K1/09 ,  H05K1/111 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/072

Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。

公开(公告)号：US09041166B2

公开(公告)日：2015-05-26

申请号：US14304988

申请日：2014-06-16

Applicant: Subtron Technology Co., Ltd.

Inventor： Ching-Sheng Chen

IPC: H01L21/00 ,  H05K3/28 ,  H05K3/06

CPC classification number: H05K3/28 ,  H05K3/062 ,  H05K2201/0338

Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer.

Abstract translation: 提供一种电路结构的制造方法。 提供具有上表面的金属层。 在金属层上形成表面钝化层。 表面钝化层暴露金属层的上表面的一部分，并且金属层的材料不同于表面钝化层的材料。 在表面钝化层上形成覆盖层，覆盖层覆盖表面钝化层。