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公开(公告)号：US20170325330A1
公开(公告)日：2017-11-09
申请号：US15176130
申请日：2016-06-07
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Ching-Sheng Chen , Ching-Ta Chen , Mei-Chin Chang
Abstract: A manufacturing method of a circuit substrate includes the following steps. A core layer having a core dielectric layer, a first patterned circuit layer and a second patterned circuit layer is provided. An electroless plating nickel layer is formed on the first patterned circuit layer and the second patterned circuit layer. The electroless plating nickel layer has a first thickness, and the first thickness is between 1 micrometer and 10 micrometers. A reducing process is performed on the electroless plating nickel layer so that the electroless plating nickel layer is thinned from the first thickness to a second thickness to form a thinned electroless plating nickel layer. The second thickness is between 0.01 micrometers and 0.9 micrometers. An electroless plating palladium layer is formed on the thinned electroless plating nickel layer. A surface metal passivation layer is formed on the electroless plating palladium layer.
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公开(公告)号：US09591753B2
公开(公告)日：2017-03-07
申请号：US14849614
申请日：2015-09-10
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Ching-Sheng Chen , Mei-Chin Chang , Ching-Ta Chen
CPC classification number: H05K1/09 , H05K1/111 , H05K3/181 , H05K3/188 , H05K3/244 , H05K2201/0338 , H05K2201/0344 , H05K2201/09472 , H05K2201/099 , H05K2203/072
Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.
Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。
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公开(公告)号：US20170013710A1
公开(公告)日：2017-01-12
申请号：US14849614
申请日：2015-09-10
Applicant: Subtron Technology Co., Ltd.
Inventor： Chin-Sheng Wang , Ching-Sheng Chen , Mei-Chin Chang , Ching-Ta Chen
CPC classification number: H05K1/09 , H05K1/111 , H05K3/181 , H05K3/188 , H05K3/244 , H05K2201/0338 , H05K2201/0344 , H05K2201/09472 , H05K2201/099 , H05K2203/072
Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.
Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。
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