公开(公告)号：DE69033443T2

公开(公告)日：2000-06-29

申请号：DE69033443

申请日：1990-05-21

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38

公开(公告)号：DE69033443D1

公开(公告)日：2000-03-09

申请号：DE69033443

申请日：1990-05-21

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38

公开(公告)号：DE69028138T2

公开(公告)日：1997-01-23

申请号：DE69028138

申请日：1990-05-21

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38

Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

公开(公告)号：AU5515490A

公开(公告)日：1990-11-29

申请号：AU5515490

申请日：1990-05-17

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38

Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

公开(公告)号：CA2016254A1

公开(公告)日：1990-11-23

申请号：CA2016254

申请日：1990-05-08

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38 ,  G06F9/22

Abstract: PAIRED INSTRUCTION PROCESSOR BRANCH RECOVERY MECHANISM A mechanism for recovering from a branch misprediction in a processor system that issues a family of more than one instruction during a single clock that determines the location of the branch instruction in the family, completes the data writes for all instructions in the family preceding the branch instruction, inhibits the data writes for all instructions in the family following the branch instruction, and fetches the correct next instruction into the pipeline. T18/10577-212

公开(公告)号：DE69028138D1

公开(公告)日：1996-09-26

申请号：DE69028138

申请日：1990-05-21

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38

Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

公开(公告)号：CA2016252A1

公开(公告)日：1990-11-24

申请号：CA2016252

申请日：1990-05-08

Applicant: TANDEM COMPUTERS INC

Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

IPC: G06F9/38 ,  G06F9/22 ,  G06F9/312

Abstract: PAIRED INSTRUCTION PROCESSOR E EXCEPTION HANDLING MECHANISM A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized. T18/10577-211

公开(公告)号：CA1215783A

公开(公告)日：1986-12-23

申请号：CA464281

申请日：1984-09-28

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT W ,  LYNCH SHANNON J ,  COSTANTINO CIRILLO L ,  BEIRNE JOHN M

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/38 ,  G06F13/38

Abstract: The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent a clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.