公开(公告)号：DE69225495D1

公开(公告)日：1998-06-18

申请号：DE69225495

申请日：1992-12-30

Applicant: TESSERA INC

Inventor： DISTEFANO THOMAS ,  KHANDROS IGOR ,  GRUBE GARY ,  EHRENBERG SCOTT

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10 ,  H05K3/02

公开(公告)号：AU6525794A

公开(公告)日：1994-10-24

申请号：AU6525794

申请日：1994-03-28

Applicant: TESSERA INC

Inventor： GRUBE GARY ,  KHANDROS IGOR ,  MATHIEU GAETAN

IPC: H01L23/48 ,  H01L23/42 ,  H01L23/44 ,  H01L23/46

Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.

公开(公告)号：DE69225495T2

公开(公告)日：1998-10-08

申请号：DE69225495

申请日：1992-12-30

Applicant: TESSERA INC

Inventor： DISTEFANO THOMAS ,  KHANDROS IGOR ,  GRUBE GARY ,  EHRENBERG SCOTT

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10 ,  H05K3/02