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    MULTILAYER CIRCUIT UNIT, ITS COMPONENT, AND MANUFACTURING METHOD THEREOF
    2.
    发明专利
    MULTILAYER CIRCUIT UNIT, ITS COMPONENT, AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：JP2002305380A

    公开(公告)日：2002-10-18

    申请号：JP2002053941

    申请日：2002-02-28

    Applicant: TESSERA INC

    Inventor： DISTEFANO THOMAS H ,  KHANDROS IGOR ,  GRUBE GARY W ,  EHRENBERG SCOTT G

    IPC: H05K1/11 ,  H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer circuit unit. SOLUTION: There are provided a first circuit panel (544) comprising a dielectric main body, a contact point (538), an electrode part (530), and a transparent conductor (527), and a second circuit panel (526) comprising a dielectric main body and an electrode part (530). The upper surface of a first circuit panel is selectively processed to customize the panel for each customer. A part of the transparent conductor of the panel is connected to a contact point of the panel. The circuit panel is laminated so that upper and lower surfaces face each other, thus the upper surface of the first circuit panel faces the lower surface of the second circuit panel at a first interface part. The first patterns on the facing surfaces center each other, while the contact point of the first panel centers a terminal of the second panel at least at a panel of the aligned pattern. All centered contact points and terminals at the interface part are non-selectively connected together, so that a part of the customized panel is connected to the terminal of an adjoining panel.

    Semiconductor chip assemblies and components with pressure contact
    10.
    发明专利
    Semiconductor chip assemblies and components with pressure contact 未知

    公开(公告)号：AU6525794A

    公开(公告)日：1994-10-24

    申请号：AU6525794

    申请日：1994-03-28

    Applicant: TESSERA INC

    Inventor： GRUBE GARY ,  KHANDROS IGOR ,  MATHIEU GAETAN

    IPC: H01L23/48 ,  H01L23/42 ,  H01L23/44 ,  H01L23/46

    Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.

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