公开(公告)号：JP2002313839A

公开(公告)日：2002-10-25

申请号：JP2002057976

申请日：2002-03-04

Applicant: TESSERA INC

Inventor： GRUBE GARY W ,  MATHIEU GAETAN ,  SWEIS JASON ,  GRANGE JOHN

IPC: H01L23/12 ,  B23K20/10 ,  H01L21/60 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor inner lead bonding method in which an operation is not affected by a little size change in a connection element. SOLUTION: The connection element having a lead is arranged on the surface of a chip such that the lead is above a contact 54. The bonding region 62 of each lead is energized down by engaging a bonding tool 60 with the contact 54 of a chip, whereas the first end, that is, base end 38 of the lead is fixed to and held by a dielectric layer structure. This lead is deformed in the shape of a letter S by moving the bonding tool 60 toward the base end, that is, the first end 38 of the lead to urge the bonding region 62 toward the first end 38 and to bend the lead, or the lead is bent down by the tool 60 and then the tool is separated from the lead to be separated from the base end 38 of the lead, and then is moved down so as to fix the lead to the contact 54 of the chip.

公开(公告)号：JP2006013501A

公开(公告)日：2006-01-12

申请号：JP2005181311

申请日：2005-06-21

Applicant: Tessera Inc ,  テセラ,インコーポレイテッド

Inventor： GRUBE GARY W ,  MATHIEU GAETAN ,  SWEIS JASON ,  GRANGE JOHN

IPC: H01L21/60 ,  H01L23/12 ,  B23K20/10 ,  H05K3/34

CPC classification number: H01L24/50 ,  B23K20/10 ,  B23K2201/40 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01082

Abstract: PROBLEM TO BE SOLVED: To provide a method for bonding electrical leads to contacts on semiconductor chips and related components, in the mounting and connection of semiconductor chips. SOLUTION: A bonding region (62) of each lead is urged downward, by engaging a tool (60) with a contact (54) on a chip, while a first or base end (38) of the lead is attached to and held by a dielectric layer structure. The lead is deformed into an S-shaped configuration, by moving the bonding tool (60) horizontally toward the base or first end (38) of the lead, thereby forcing the bonding region (62) toward the first end (38) and bending the lead. Alternatively, the lead is bent downward by the tool, and then the tool is separated from the lead, is shifted away from the base end (38) of the lead, and is further moved downward to secure the lead to the chip contact (54). COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于将半导体芯片的安装和连接中的电引线接合到半导体芯片和相关部件上的触点的方法。 解决方案：通过将工具（60）与芯片上的触点（54）接合在一起，引线的接合区域（62）被向下推动，同时引线的第一或基端（38）附接到 并由介电层结构保持。 通过使接合工具（60）水平地朝向引线的基部或第一端（38）移动，引线变形为S形构造，从而迫使接合区域（62）朝向第一端（38）并弯曲 带头。 或者，引线通过工具向下弯曲，然后工具与引线分离，从引线的基端（38）移开，并进一步向下移动以将引线固定到芯片接触（54 ）。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：AU6525794A

公开(公告)日：1994-10-24

申请号：AU6525794

申请日：1994-03-28

Applicant: TESSERA INC

Inventor： GRUBE GARY ,  KHANDROS IGOR ,  MATHIEU GAETAN

IPC: H01L23/48 ,  H01L23/42 ,  H01L23/44 ,  H01L23/46

Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.