公开(公告)号：WO2016073460A1

公开(公告)日：2016-05-12

申请号：PCT/US2015/058802

申请日：2015-11-03

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  CHEN, Renjie

IPC: H01L21/20 ,  H01L21/3213 ,  H01L21/447

CPC classification number: H01L24/83 ,  G02B6/13 ,  H01L21/185 ,  H01L21/187 ,  H01L21/28575 ,  H01L21/8252 ,  H01L21/8258 ,  H01L24/29 ,  H01L27/0605 ,  H01L2224/29082 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/29187 ,  H01L2224/83203 ,  H01L2224/8383 ,  H01L2924/05042 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/20107 ,  H01S5/0215

Abstract: A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.

Abstract translation: 将III-V半导体材料集成到刚性主体衬底上的方法在刚性主体衬底上沉积薄层的反应性金属膜。 该层还可以包括非反应性金属或电介质的分离层，并且可以被图案化。 接合完成后，非反应性金属图案可以产生自对准的器件触点。 III-V族半导体材料与薄层的反应性金属接触。 粘合是通过在压缩压力下的低温热处理。 选择反应性金属和功能性半导体材料进行固相反应，并在低温热处理下形成稳定的合金，而不降解III-V材料。 本发明的半导体器件包括通过功能III-V层的组分与键合到刚性衬底的金属的合金结合到刚性衬底的功能III-V层。

公开(公告)号：WO2016145220A1

公开(公告)日：2016-09-15

申请号：PCT/US2016/021814

申请日：2016-03-10

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  RO, Yun Goo ,  PARK, Namseok ,  TANAKA, Atsunori ,  VISHNIAKOU, Siarhei ,  YOUSSEF, Ahmed ,  BUCKWALTER, James ,  LEVY, Cooper

IPC: A61B5/04 ,  A61B5/0408 ,  H01L21/8238 ,  H01L27/142

CPC classification number: H01L27/142 ,  A61B5/0402 ,  A61B5/0476 ,  A61B5/0488 ,  A61B5/6802 ,  A61B2560/0214 ,  A61B2562/028 ,  A61B2562/125 ,  A61B2562/164 ,  B81B2201/0214 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L31/042 ,  H02S40/44

Abstract: Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.

Abstract translation: 将诸如环境传感器，电池和生物传感器的薄膜元件/器件单片集成到具有高性能集成电路，即在高质量器件层中形成的集成电路的方法和装置。 优选的实施例进一步整合了太阳能电池阵列。 优选实施例提供引脚尺寸和集成的太阳能驱动的可佩戴的电子，离子，分子，辐射等传感器和电路。

公开(公告)号：WO2016022906A1

公开(公告)日：2016-02-11

申请号：PCT/US2015/044185

申请日：2015-08-07

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  AZZAZY, Farid ,  LEE, Sang Heon

IPC: A61B5/04

CPC classification number: A61B5/0478 ,  B81B1/00 ,  B81B2201/0292 ,  B81B2203/0361 ,  B81B2203/04 ,  B81C1/00111 ,  B81C2201/013

Abstract: A preferred conformal penetrating multi electrode array includes a plastic substrate that is flexible enough to conform to cortical tissue. A plurality of penetrating semiconductor micro electrodes extend away from a surface of the flexible substrate and are stiff enough to penetrate cortical tissue. Electrode lines are encapsulated at least partially within the flexible substrate and electrically connected to the plurality of penetrating semiconductor microelectrodes. The penetrating semiconductor electrodes preferably include pointed metal tips. A preferred method of fabrication permits forming stiff penetrating electrodes on a substrate that is very flexible, and providing electrical connection to electrode lines within the substrate.

Abstract translation: 优选的共形穿透性多电极阵列包括足够柔性以符合皮质组织的塑料基底。 多个穿透半导体微电极远离柔性基底的表面延伸并且足够硬以穿透皮质组织。 电极线至少部分地封装在柔性基板内并电连接到多个穿透半导体微电极。 穿透半导体电极优选地包括尖锐的金属尖端。 优选的制造方法允许在非常柔性的基底上形成刚性穿透电极，并且提供与衬底内的电极线的电连接。

公开(公告)号：WO2019089727A1

公开(公告)日：2019-05-09

申请号：PCT/US2018/058407

申请日：2018-10-31

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  CHOI, Woojin ,  CHEN, Renjie ,  TANAKA, Atsunori ,  LIU, Ren

IPC: H01L29/02 ,  H01L29/778 ,  H01L27/092

CPC classification number: H01L29/7786 ,  H01L29/0657 ,  H01L29/2003

Abstract: Devices and methods of the invention use a plurality of Fin structures and or combine a planar portion with Fin structures to compensate for the first derivative of transconductance, gm. In preferred methods and devices, Fins have a plurality of widths and are selected to lead to the separate turn-on voltage thresholds for the largest, intermediate and smallest widths of the MIS HEMT fins to flatten the transconductance gm curve over an operational range of gate source voltage.

公开(公告)号：WO2022192560A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/019778

申请日：2022-03-10

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  TCHOE, Youngbin ,  BOURHIS, Andrew M.

IPC: A61N1/05 ,  A61N1/18 ,  H01L21/768 ,  H05K1/02 ,  H05K3/02 ,  H05K3/42 ,  H01L51/42

Abstract: A flexible electrode array with hundreds or thousands channels for clinical use includes an array of at least hundreds of electrodes on a flexible biocompatible polymer substrate. Perfusion through holes are provided through the substrate. Individual elongate leads connect to each of the electrodes, the elongate lead connections being supported by the flexible biocompatible polymer substrate and extending away from the array. Flexible biocompatible polymer insulates the individual elongate lead connections and supporting the array. An interposer with individual channel connections is conductively bonded to the individual elongate lead connections. Sterile bag packaging encloses a portion of the interposer, where the outer side of the package including the array and individual elongate lead is sterile while the inner side of the packaging is non-sterile. The portion interposer inside the package is configured to connect to a circuit board within the packaging.

公开(公告)号：WO2022035659A1

公开(公告)日：2022-02-17

申请号：PCT/US2021/044520

申请日：2021-08-04

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  OH, Hongseok

IPC: G01L1/16 ,  G01L9/08 ,  H01L27/01 ,  H01L29/786 ,  H04R17/00

Abstract: A flexible thin film transistor tactile sensor includes a piezoelectric semiconductor thin film channel of material whose conductivity can be electrostatically controlled connected with source and drain metals and sandwiched between bottom and top thin film insulators and at least one of a bottom and top gate metal, the sensor being supported on a flexible substrate. The piezoelectric property of the used material transduces pressure to electronic charge. The semiconductor property of the used material permits electrostatic modulation of the conductivity in TFT device architecture such that the device can be switched on and off. Transistor action provides gain for input signals, i.e., a modulation of the gate voltage induces strong current change between the source and drain, which can be leveraged to amplify the response to input pressure. The transistor forms the basis for sensor arrays, which are readily scalable to large size.

公开(公告)号：WO2017127551A1

公开(公告)日：2017-07-27

申请号：PCT/US2017/014143

申请日：2017-01-19

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： DAYEH, Shadi A. ,  CHEN, Renjie ,  LEE, Sang Heon ,  LIU, Ren ,  RO, Yun Goo ,  TANAKA, Atsunori ,  HWANG, Yoontae

IPC: B82B3/00 ,  B82B1/00 ,  B82Y5/00 ,  B82Y15/00 ,  A61B5/042 ,  A61B5/04

CPC classification number: A61B5/04001 ,  A61B2562/0285 ,  A61B2562/046 ,  A61B2562/125 ,  B81B2201/055 ,  B81C1/00111 ,  B82Y15/00

Abstract: A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.

Abstract translation: 纳米线探针传感器阵列，包括其上具有金属图案的衬底。 半导体垂直纳米线探针的阵列从衬底延伸出来，并且探针中的至少一些，并且优选地全部通过金属图案单独电寻址。 金属图案用电介质绝缘，并且纳米线的基部和杆部也优选地绝缘。 制造工艺在衬底上图案化金属连接。 半导体衬底结合到金属图案。 蚀刻半导体衬底以形成结合到金属图案的神经纳米线探针。 然后沉积电介质以绝缘金属图案。