公开(公告)号：JP2011044554A

公开(公告)日：2011-03-03

申请号：JP2009191259

申请日：2009-08-20

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUJISAWA TADAHITO

IPC: H01L21/027 ,  G03F7/207

CPC classification number: G03F7/70425 ,  G03F7/70525

Abstract: PROBLEM TO BE SOLVED: To provide an exposure control apparatus for exposing a shot of a wafer circumference with high yield and high efficiency.
SOLUTION: The exposure control apparatus includes an exposure presence-setting unit 12 that performs an exposure setting of setting an exposure shot as a shot that is exposed or a shot that is not exposed based on height information on a height of the wafer in the exposure shot arranged in the after circumference, and an exposure instructing unit 14 that outputs an exposure instruction to the shot that is exposed and an instruction to skip an exposure to the shot that is not exposed by the exposure presence-setting unit 12.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于以高产率和高效率曝光晶片圆周的镜头的曝光控制装置。 解决方案：曝光控制装置包括：曝光存在设置单元12，其执行曝光设置，其将拍摄的曝光设置为曝光的镜头或基于高度信息的未曝光的镜头在晶片的高度上 在后周围布置的曝光镜头中，以及曝光指令单元14，其向曝光的镜头输出曝光指令，以及忽略曝光存在设置单元12未曝光的镜头的曝光指令。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008020714A

公开(公告)日：2008-01-31

申请号：JP2006192867

申请日：2006-07-13

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUJISAWA TADAHITO ,  ITO KENJI ,  YANAI YOSHIHIRO ,  MAEZONO ATSUSHI ,  FUKUHARA KAZUYA

IPC: G03F1/32 ,  G03F1/68 ,  H01L21/027

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: PROBLEM TO BE SOLVED: To form a desired fine pattern with less dimensional variation.
SOLUTION: In a region where a semitransmissive region Tb, a transmissive region Ta, and a light-shielding portion S are successively disposed along a longitudinal direction of a L/S pattern from an end portion Ma of a memory cell region M positioned in the center of the entire region Z of the pattern, wherein a dimension in a width direction of the L/S pattern in the semitransmissive region Tb is set larger with the shorter the distance from the semitransmissive region Tb to the light-shielding portion S.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：形成具有较小尺寸变化的所需精细图案。 解决方案：在半导体区域Tb，透射区域Ta和遮光部分S沿着L / S图案的纵向方向从存储单元区域M的端部Ma连续布置的区域中 位于图案的整个区域Z的中心，其中，在半透射区域Tb中的L / S图案的宽度方向上的尺寸被设定为随着从半透射区域Tb到遮光部分的距离越短 （C）2008，JPO＆INPIT

公开(公告)号：JP2006245539A

公开(公告)日：2006-09-14

申请号：JP2005356796

申请日：2005-12-09

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUTAYAMA TAKUYA ,  KOTANI TOSHIYA ,  MASHITA HIROMITSU ,  MAEZONO ATSUSHI ,  NAKANO AYAKO ,  FUJISAWA TADAHITO

IPC: H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11517

Abstract: PROBLEM TO BE SOLVED: To realize a NAND-type flash memory with a high reliability.
SOLUTION: This invention relates to a semiconductor memory device which is provided with at least a first wiring layer and a second wiring layer in order at an upper layer than a gate wiring and can electrically write data in a memory cell, wherein the memory cell has a word line and a bit line, and the word line connected to the memory cell is formed by the gate wiring, and the word line is connected by using a three-layer wiring comprising the gate wiring, the first wiring layer and the second wiring layer when the word line is connected to a source or a drain of a first transistor, and in a connection region a maximum potential difference between fellow gate wirings is not greater than a writing voltage, and a maximum potential difference between fellow first wirings is not greater than the writing voltage or is not greater than a first voltage for transmitting the writing voltage by means of the first transistor, and a maximum potential difference between fellow second wiring layers is not greater than the writing voltage or an erasing voltage.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：实现具有高可靠性的NAND型闪存。 半导体存储器件本发明涉及一种半导体存储器件，该半导体存储器件在上层设置有至少第一布线层和第二布线层，而不是栅极布线，并且可以将数据电写入存储单元，其中， 存储单元具有字线和位线，并且连接到存储单元的字线由栅极布线形成，并且字线通过使用包括栅极布线，第一布线层和第三布线的三层布线连接 当字线连接到第一晶体管的源极或漏极时，第二布线层，并且在连接区域中，栅极配线之间的最大电位差不大于写入电压，并且第一晶体管的最大电位差 布线不大于写入电压或者不大于通过第一晶体管传输写入电压的第一电压，并且第二布线1a之间的最大电位差 yers不大于写入电压或擦除电压。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005026362A

公开(公告)日：2005-01-27

申请号：JP2003188496

申请日：2003-06-30

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： HAYAZAKI KEI ,  MUTO DAIZO ,  ASANO MASASHI ,  FUJISAWA TADAHITO ,  SHIBATA TAKESHI ,  ITO SHINICHI

IPC: G03F7/26 ,  G03F7/20 ,  G03F7/40 ,  H01L21/027 ,  H01L23/544

CPC classification number: G03F7/70683 ,  G03F7/40

Abstract: PROBLEM TO BE SOLVED: To restrain the changing of effectual light exposure between apparatuses which a photopolymer film obtained by the difference of temperatures between the apparatuses. SOLUTION: The temperature proofreading method of a heat treatment apparatus is provided with a process for preparing a plurality of the heat treatment apparatuses, a process wherein a substrate with a light exposure monitor pattern formed is subjected to heat treatment at a plurality of setting temperatures in each of the prepared heat treatment apparatuses, a process for measuring the status of the light exposure monitor pattern at either after cooling treatment or after development processing, a process for obtaining a relation between a setting temperature and effectual light exposure about each of the heat treatment apparatuses from a plurality of the setting temperatures and the measured status of the light exposure monitor pattern, and a process wherein the setting temperature is corrected so that predetermined effectual light exposure is obtained about each of the heat treatment apparatuses from the obtained relation. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：抑制通过设备之间的温度差获得的光聚合物膜的设备之间的有效曝光的变化。 解决方案：热处理设备的温度校正方法具有制备多个热处理设备的方法，其中形成有曝光监视器图案的基板在多个处理装置中进行热处理 每个制备的热处理设备中的设定温度，在冷却处理之后或显影处理之后测量曝光监视器图案的状态的处理，获得设置温度和有效曝光之间的关系的处理 来自多个设定温度的热处理设备和曝光监视器图案的测量状态，以及其中校正设定温度使得从每个热处理设备获得关于每个热处理设备的预定有效曝光的处理 。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004200600A

公开(公告)日：2004-07-15

申请号：JP2002370502

申请日：2002-12-20

Applicant: Nikon Corp ,  Shin Etsu Handotai Co Ltd ,  Toshiba Corp ,  信越半導体株式会社 ,  株式会社ニコン ,  株式会社東芝

Inventor： FUJISAWA TADAHITO ,  INOUE SOICHI ,  KOBAYASHI MAKOTO ,  ICHIKAWA MASASHI ,  HAGIWARA TSUNEYUKI ,  KODAMA KENICHI

IPC: H01L21/66 ,  G01B11/30 ,  H01L21/027 ,  H01L21/302 ,  H01L21/461

CPC classification number: G01B21/30 ,  G01B11/306 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a wafer-flatness evaluation method whereby the flatnesses present in the surface of a wafer can be evaluated in the state closer to a flatnesses which an exposure device can sense. SOLUTION: The wafer-flatness evaluation method has a process (300) for measuring the front and rear surface shapes of a wafer, a process (301) for partitioning the front and rear surfaces of the wafer into their sites, processes (302, 303, 304, 305) for selecting wafer-flatness calculating ways in response to the positions of the valuing sites, and a process (306) for acquiring the flatnesses present in the surface of the wafer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2000021732A

公开(公告)日：2000-01-21

申请号：JP18762498

申请日：1998-07-02

Applicant: TOSHIBA CORP

Inventor： SATO KAZUYA ,  TANAKA SATOSHI ,  FUJISAWA TADAHITO ,  INOUE SOICHI

IPC: G03F7/20 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To test an aligner promptly in a simple way, without disassembling the aligner. SOLUTION: In this testing method, an aligner consists of a light source, a lighting optical system 1 for conducting the light from the light source to a photo mask, and a projection optical system 3 for transferring a reduced image onto a wafer 5. The testing method is user for testing the configuration of light source of the aligner, a configuration of a pupil 4 in the projection optical system 3, and a degree of concentricity between the light source configuration and the pupil 4. The light from the light source is irradiated the reticle 2 with lattice pattern, in which light transmitting and shielding parts are repeated in a finite cycle. Then, an outer edge of the pupil 4 in the projection optical system 3 is irradiated with light with first or higher orders of diffraction, and at the same time, a pattern image of the reticle 2 in a defocused state is exposed on the wafer 5.

公开(公告)号：JPH06267822A

公开(公告)日：1994-09-22

申请号：JP5670593

申请日：1993-03-17

Applicant: TOSHIBA CORP

Inventor： TANAKA SATOSHI ,  INOUE SOICHI ,  FUJISAWA TADAHITO

IPC: G03F1/00 ,  G03F1/68 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H01L21/30 ,  G03F1/08

Abstract: PURPOSE:To obtain a fine contact hole pattern group, by forming patterns periodically in two directions on the mask surface, forming phase difference in the lights passing neighboring patterns, and making the emission surface light intensity of a light source large in the region distant from the optical axis. CONSTITUTION:The reticle 5 has 5 an optical shielding part 9 which does not transmit exposure light, and an aperture part 10 which transmits the exposure light, on a transparent substrate. A phase shifter part 11 formed by digging the substrate in the aperture part is arranged. The phase shifter part 11 is so formed that the phase difference of light passing the part 11 becomes nearly 180 deg. with respect to the aperture part 10. A light source filter 8 consists of an optical shielding part 12 and a light transmitting part 13, and the optical shielding part 12 has a form of four times symmetry regarding an optical axis 22. When the reticle 5 is irradiated with the light from a point light source 14, light flux interference is caused on a wafer 7 by four diffraction light beams, and light intensity distribution is similar to the distribution obtained by two times exposure of the phase shift mask. Hence it is unnecessary that the exposure is again performed by changing masks, and high resolution exposure is possible.

公开(公告)号：JP2012060142A

公开(公告)日：2012-03-22

申请号：JP2011233328

申请日：2011-10-24

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： MASHITA HIROMITSU ,  KOTANI TOSHIYA ,  MAEZONO ATSUSHI ,  NAKANO AYAKO ,  FUJISAWA TADAHITO

IPC: H01L27/115 ,  G03F1/68 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8247 ,  H01L23/52 ,  H01L27/04 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which comes with a group of wiring patterns including multiple wiring patterns effective for high integration.SOLUTION: There is included a group of wiring patterns including N (N≥3) lengths of wiring patterns used for the same wiring purpose. The N lengths of wiring patterns respectively include a connection region for electrically connecting to wiring patterns in a wiring group in another layer. The N lengths of wiring patterns include a wiring pattern N1 and two or more wiring patterns Ni (i≥2) disposed in one direction differing from the longer direction of the wiring pattern N1. The two or more wiring patterns Ni are disposed at increasingly distant positions from the wiring pattern N1 as the value i increases, and they include at least one or more wiring patterns Np (2≤p

Abstract translation: 要解决的问题：提供一种具有一组布线图案的半导体器件，其包括有效地用于高集成度的多个布线图案。

解决方案：包括一组布线图案，包括用于相同布线目的的N（N≥3）个长度的布线图案。 布线图案的N个长度分别包括用于电连接到另一层中的布线组中的布线图案的连接区域。 布线图案的N个长度包括布线图案N1和布置在与布线图案N1的长度方向不同的一个方向上的布线图案Ni（i≥2）。 两个以上的配线图案Ni随着值i增加而配置在与布线图案N1越来越远的位置，并且它们包括至少一个或多个布线图案Np（2≤p

公开(公告)号：JP2009123878A

公开(公告)日：2009-06-04

申请号：JP2007295627

申请日：2007-11-14

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ITO KENJI ,  YANAI YOSHIHIRO ,  FUJISAWA TADAHITO ,  HAYASHI KENJI

IPC: H01L21/027 ,  G03F1/00 ,  G03F1/70 ,  G03F7/20 ,  G03F7/40

Abstract: PROBLEM TO BE SOLVED: To excellently form a fine pattern at a close pitch almost to or below a resolution limit.
SOLUTION: In a method of forming a plurality of line-and-space pattern on a base material film 1, the method includes the steps of: forming a first exposure mask having first light transparent parts formed corresponding to alternate first space parts; forming a second exposure mask having second light transparent parts formed corresponding to the remaining first space parts; transferring a first exposure mask pattern and a second exposure mask pattern to a resist film formed on the base material film 1; forming a resist pattern by developing the resist film; burying a framing material film in the second space parts of the resist pattern; forming a bridge layer as a coating layer of the second line part through a heat treatment; and forming the line-and-space pattern by removing a non-bridge part of the framing material.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了以几乎等于或低于分辨率极限的接近间距精细地形成精细图案。 解决方案：在基材薄膜1上形成多个线间距图案的方法中，该方法包括以下步骤：形成第一曝光掩模，该第一曝光掩模具有对应于交替的第一空间部分形成的第一透光部分 ; 形成具有对应于剩余的第一空间部分形成的第二透光部分的第二曝光掩模; 将第一曝光掩模图案和第二曝光掩模图案转印到形成在基材膜1上的抗蚀剂膜; 通过显影抗蚀剂膜形成抗蚀剂图案; 将掩模材料膜埋在抗蚀图案的第二空间部分中; 通过热处理形成桥接层作为第二管线部分的涂层; 以及通过去除框架材料的非桥接部分来形成线间距图案。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007150166A

公开(公告)日：2007-06-14

申请号：JP2005345529

申请日：2005-11-30

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUJISAWA TADAHITO ,  ITO KENJI ,  HASHIMOTO KOJI

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To form a pattern within limits of lithography by effectively using a side wall machining process even for various fine hole patterns having random patterns in addition to periodic patterns.
SOLUTION: The method of manufacturing a semiconductor device using the side wall machining process comprises a step of forming a first sacrificial film which has a period twice as long as that of a desired sacrificial film pattern, and whose line consists of a line and a space thinner than a space on a processed film 11; forming a second sacrificial film 15 on a flank part of the first sacrificial film, and then removing the first sacrificial film; then forming a resist pattern 16 for processed film on the processed film 11 and second sacrificial film 15; and selectively etching the processed film 11 by using the resist pattern 16 and second sacrificial film 15 as a mask to form a hole pattern.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：即使对于具有除了周期性图案之外的随机图案的各种细孔图案，通过有效地使用侧壁加工工艺来在光刻的限度内形成图案。 解决方案：使用侧壁加工工艺制造半导体器件的方法包括形成第一牺牲膜的步骤，该第一牺牲膜的周期是期望的牺牲膜图案的两倍，并且其线由一条线 和比加工膜11上的空间薄的空间; 在第一牺牲膜的侧面部分上形成第二牺牲膜15，然后去除第一牺牲膜; 然后在处理膜11和第二牺牲膜15上形成用于加工膜的抗蚀剂图案16; 并且通过使用抗蚀剂图案16和第二牺牲膜15作为掩模来选择性地蚀刻经处理的膜11以形成孔图案。 版权所有（C）2007，JPO＆INPIT