公开(公告)号：JPS5948767A

公开(公告)日：1984-03-21

申请号：JP15743482

申请日：1982-09-11

Applicant: Toshiba Corp

Inventor： KASAHARA MASAO ,  SASAGAWA HIROMOTO

IPC: G03F1/00 ,  G03F1/40 ,  G03F1/54 ,  H01L21/027 ,  H01L21/30

CPC classification number: H01L21/30

Abstract: PURPOSE:To carry out microscopic inspection efficiently without causing electrostatic breakdown, by electrically short-circuiting a pattern with a nontransfer conductive film part on its outside through conductive wires. CONSTITUTION:The conductive film part 1 of the outer circumference of a mask substrate is electrically connected with the conductive film part 2 in its inside for use in transfer through the conductive wires 3 formed on the inside of the part 1, and all the parts 2 arranged along the wires 3 are connected through the wires 3. As a result, charge generated at each part 2 moves to the part 1, and accumulation of the charge and discharge breakdown can be prevented. Since the wires 3 can be used as a scanning coordinate axis at the time of microscopic inspection by arranging each of the wires 3 in parallel to each other at each row of the parts 3, the location of defect occurring at the parts 2 can be detected as a coordinate value, and the microscopic inspection can be carried out efficiently, too.

Abstract translation: 目的：通过导电线将外部非转移导电膜部件的图案电气短路，从而有效地进行显微镜检查而不引起静电破坏。 构成：掩模基板的外周的导电膜部1与其内部的导电膜部2电连接，用于通过形成在部件1的内部的导电线3传递，并且所有部件2 沿着导线3布置的布线3通过导线3连接。结果，在每个部分2处产生的电荷移动到部分1，并且可以防止充电和放电击穿的累积。 由于通过在部件3的每一排布置各个电线3彼此平行，因此可以在显微检查时将电线3用作扫描坐标轴，因此可以检测在部件2处发生的缺陷的位置 作为坐标值，也可以有效地进行显微镜检查。

公开(公告)号：JPH02303221A

公开(公告)日：1990-12-17

申请号：JP12361489

申请日：1989-05-17

Applicant: TOSHIBA CORP

Inventor： MORII MASAKATSU ,  KASAHARA MASAO ,  KODAMA TOMOKO ,  NAKAMURA MAKOTO

IPC: G06F11/10 ,  H03M13/00

Abstract: PURPOSE:To quicken the decoding processing by varying a series of decoding procedures obtaining an error location polynomial and an error numeral polynomial from a residue polynomial in various kinds of ways. CONSTITUTION:A reception symbol R(X) is inputted from an input terminal 1 and supplied to a residue calculation circuit 2 and a storage circuit 3. A fundamental equation arithmetic circuit 4 receives a residue obtained from the residue calculation circuit 2 to obtain coefficients of two polynomials W(X), N(X). The coefficient of the equation W(X) calculated by the fundamental equation arithmetic circuit 4 is fed to an error location calculation circuit 5. When a reed Solomon code is generated by a generation polynomial, number of data stored in a storage circuit 10 is decreased. An error correction circuit 7 corrects an error of reception series to given an output to an output terminal 8.