公开(公告)号：JPH02303221A

公开(公告)日：1990-12-17

申请号：JP12361489

申请日：1989-05-17

Applicant: TOSHIBA CORP

Inventor： MORII MASAKATSU ,  KASAHARA MASAO ,  KODAMA TOMOKO ,  NAKAMURA MAKOTO

IPC: G06F11/10 ,  H03M13/00

Abstract: PURPOSE:To quicken the decoding processing by varying a series of decoding procedures obtaining an error location polynomial and an error numeral polynomial from a residue polynomial in various kinds of ways. CONSTITUTION:A reception symbol R(X) is inputted from an input terminal 1 and supplied to a residue calculation circuit 2 and a storage circuit 3. A fundamental equation arithmetic circuit 4 receives a residue obtained from the residue calculation circuit 2 to obtain coefficients of two polynomials W(X), N(X). The coefficient of the equation W(X) calculated by the fundamental equation arithmetic circuit 4 is fed to an error location calculation circuit 5. When a reed Solomon code is generated by a generation polynomial, number of data stored in a storage circuit 10 is decreased. An error correction circuit 7 corrects an error of reception series to given an output to an output terminal 8.