公开(公告)号：JP2010026330A

公开(公告)日：2010-02-04

申请号：JP2008189069

申请日：2008-07-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI SATOSHI ,  HASHIMOTO KOJI

IPC: G03F1/84 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide a pattern inspection method for accurately and efficiently detecting a side lobe.
SOLUTION: This pattern inspection method includes a process S12 for shifting an edge of a design pattern defined in data into the outside direction of the design pattern, a process S14 for defining an inspection region in the data based on the region where the edge is shifted, a process S16 for transferring a circuit pattern based on the design pattern onto a substrate, and a process S17 for inspecting the region being the region on the substrate having the transferred circuit pattern and corresponding to the inspection region.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供用于准确有效地检测旁瓣的图案检查方法。 解决方案：该图案检查方法包括：将数据中定义的设计图案的边缘移位到设计图案的外部方向的处理S12，用于基于区域中定义数据中的检查区域的处理S14， 边缘移动，用于将基于设计图案的电路图案转印到基板上的处理S16以及用于检查具有转印电路图案并且对应于检查区域的具有转印电路图案的基板上的区域的区域的处理S17。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2002318448A

公开(公告)日：2002-10-31

申请号：JP2001124683

申请日：2001-04-23

Applicant: TOSHIBA CORP

Inventor： HASHIMOTO KOJI ,  INOUE SOICHI ,  TANAKA SATOSHI ,  USUI SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a pattern correcting method for a mask for exposure, by which a new OPC(operations planning and control) rule or the like can be created in a short time in case of any change in a unit process after an OPC rule or the like is determined. SOLUTION: In the case of any change in part of a plurality of unit processes (e.g. mass processes) constituting a unit process group, an OPC rule/model is newly set on the basis of proximity effect data before and after the change on the unit process subjected to the change and proximity effect correction of the pattern of a mask for exposure is carried out.

公开(公告)号：JP2009182237A

公开(公告)日：2009-08-13

申请号：JP2008021405

申请日：2008-01-31

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI SATOSHI ,  TANAKA SATOSHI

IPC: H01L21/027 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F7/70625 ,  G03F7/705

Abstract: PROBLEM TO BE SOLVED: To provide a technology capable of improving the manufacture yield of a semiconductor integrated circuit. SOLUTION: The exposure condition setting method includes: a step (ST1) of inputting design layout data; a step of extracting a plurality of gate patterns having a prescribed gate length from the inputted design layout data; a step (ST2) of calculating the dimension variation amount of a transfer pattern transferred and formed on a film to be transferred by exposing a mask pattern corresponding to the extracted gate patterns and the design value of the gate patterns; a step (ST3) of obtaining the distribution of the number of the gate patterns corresponding to the dimension variation amount of the gate patterns; and a step (ST4) of setting an exposure condition so that the dimension variation amount of the gate pattern indicating the mode or median of the gate pattern number distribution satisfies the condition of permission. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供能够提高半导体集成电路的制造成品率的技术。 曝光条件设定方法包括：输入设计布局数据的步骤（ST1）; 从输入的设计布局数据提取具有规定的栅极长度的多个栅极图案的步骤; 计算通过曝光与所提取的栅极图案相对应的掩模图案和栅极图案的设计值来转印和形成的要传送的膜上的转印图案的尺寸变化量的步骤（ST2） 获得与栅极图案的尺寸变化量对应的栅极图案的数量分布的步骤（ST3）; 以及设定曝光条件的步骤（ST4），使得指示栅极图案数量分布的模式或中值的栅极图案的尺寸变化量满足许可条件。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2012164811A

公开(公告)日：2012-08-30

申请号：JP2011023999

申请日：2011-02-07

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： NISHIO HIROYUKI ,  USUI SATOSHI

IPC: H01L21/027 ,  G03F1/84

CPC classification number: G03F1/84 ,  G03F1/70

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which reduction in yield can be suppressed by reducing misalignment of a pattern formed using an exposure mask and a pattern formed in the process of matching destination, and to provide a method of determining the shipping of exposure masks and a method of manufacturing the exposure mask.SOLUTION: A first mask having a first pattern including a misalignment measurement pattern after exposure, and a pattern in a main integrated circuit is manufactured. Displacement of the misalignment measurement pattern after exposure, and displacement of the pattern in the main integrated circuit in the first pattern are measured, respectively, and a first difference, i.e. the difference of these displacements, is calculated. The first difference is reflected on the alignment parameters when a wafer is subjected to exposure processing using the first mask.

Abstract translation: 要解决的问题：提供一种制造半导体器件的方法，其中通过减少使用曝光掩模形成的图案的不对准以及在匹配目的地的过程中形成的图案，可以抑制产量的降低，并且提供 确定曝光掩模的运送的方法和制造曝光掩模的方法。 解决方案：制造具有包括曝光后的未对准测量图案的第一图案的第一掩模和主集成电路中的图案。 测量曝光后的未对准测量图案的位移和第一图案中的主集成电路中的图案的位移，并且计算第一差，即这些位移的差。 当使用第一掩模对晶片进行曝光处理时，第一个差异反映在对准参数上。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2012089635A

公开(公告)日：2012-05-10

申请号：JP2010234194

申请日：2010-10-19

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI SATOSHI

IPC: H01L21/027 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device and a program capable of identifying high-risk systematic defects.SOLUTION: A manufacturing method of a semiconductor device according to an embodiment comprises: a step (1) of manufacturing wafers in which a plurality of exposure regions where an exposure amount was changed in one direction and a focus amount was changed in another direction were arranged in a matrix state; a step (2) of inspecting whether the wafers are defective; a step (3) of identifying whether the defects detected in the step (2) of identifying whether the wafers are defective are systematic defects; and a step (4) of ranking the risk degree of the identified systematic defects based on the exposure conditions under which the systematic defects occur.

Abstract translation: 要解决的问题：提供半导体器件的制造方法和能够识别高风险系统缺陷的程序。 解决方案：根据实施例的半导体器件的制造方法包括：制造晶片的步骤（1），其中曝光量在一个方向上变化的多个曝光区域和焦点量在另一个方向上改变 方向排列成矩阵状态; 检查晶片是否有缺陷的步骤（2）; 识别在步骤（2）中检测到的用于识别晶片是否有缺陷的缺陷的步骤（3）是系统缺陷; 以及基于所发生的系统缺陷的暴露条件来对所识别的系统缺陷的风险程度进行排序的步骤（4）。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2008066666A

公开(公告)日：2008-03-21

申请号：JP2006245909

申请日：2006-09-11

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI SATOSHI ,  HASHIMOTO KOJI

IPC: H01L21/66 ,  G01N21/93 ,  G01N21/956

CPC classification number: G06K9/4604 ,  G06K2209/19

Abstract: PROBLEM TO BE SOLVED: To provide a calibration method, an inspection method, and a method of manufacturing a semiconductor device by which a pattern edge can be extracted accurately.
SOLUTION: In the calibration method as an embodiment of the present invention, a threshold (S) is calibrated when a pattern edge is extracted from an image having a pattern formed on a substrate to be processed. The contrast of the image including parts (21, 22) expected to be defective in the pattern is calculated, and the threshold is calibrated so as not to extract, based on the contrast, a pattern edge on the parts expected to be defective.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供校准方法，检查方法和制造可精确提取图案边缘的半导体器件的方法。 解决方案：在作为本发明的实施例的校准方法中，当从具有形成在待处理的衬底上的图案的图像中提取图案边缘时，校准阈值（S）。 计算包括期望在图案中有缺陷的部分（21,22）的图像的对比度，并且校准该阈值，以便基于对比度不提取预期为有缺陷的部件上的图案边缘。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002006475A

公开(公告)日：2002-01-09

申请号：JP2000187867

申请日：2000-06-22

Applicant: TOSHIBA CORP

Inventor： NOJIMA SHIGEKI ,  USUI SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for designing a mask pattern which can perform strict pattern correction and to provide a mask formed by the method. SOLUTION: An original design pattern is altered till difference between an objective pattern and a simulation pattern becomes below a specified value. Difference between the altered original design pattern and the objective pattern is extracted and a plus/minus correction layer is produced. Then OPC correction to the altered original design pattern is performed and an OPC correction pattern is formed. The mask pattern is formed by synthesizing the plus/minus correction layer with the OPC correction pattern.

公开(公告)号：JP2001092112A

公开(公告)日：2001-04-06

申请号：JP27134299

申请日：1999-09-24

Applicant: TOSHIBA CORP

Inventor： USUI SATOSHI ,  HASHIMOTO KOJI

IPC: G03F1/36 ,  G03F1/72 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for correcting a mask pattern by which correction of the mask can be made with high precision by using electric measurement with respect to OPE. SOLUTION: TEG for deriving a correction table is produced (S101) and electrical resistance is measured (S102). Then, a correction factor (S103) which is first-order correlation coefficient of electrical resistance to the wiring width and design specification variation (S104) are calculated at every wiring width and every wiring space. The design dimension variation is interpolated to the wiring space (S105) and is converted to a design dimension correction quantity (S106) and wiring space value giving integer value is extracted (S107). Thereby a correction table used for correction of the mask pattern is prepared (S108).

公开(公告)号：JP2000010254A

公开(公告)日：2000-01-14

申请号：JP17299098

申请日：1998-06-19

Applicant: TOSHIBA CORP

Inventor： TAKAHATA KAZUHIRO ,  USUI SATOSHI ,  KUJI TATSUAKI ,  HASHIMOTO KOJI

IPC: G01B11/00 ,  G03F1/29 ,  G03F1/32 ,  G03F1/68 ,  G03F9/00 ,  H01L21/027 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To make it possible to obtain pattern shapes of misalignment measurement marks which do not affect a misalignment detection signal by disposing the misalignment measurement marks consisting of at least two space patterns of the same width formed in parallel along the longitudinal direction of line patterns adjacently to at least one line patterns. SOLUTION: The misalignment measurement marks for forming the space patterns constituting outer marks 2, 2a to a resist film on a semiconductor substrate 4 are formed on a halftone film. The misalignment measurement marks are formed by forming inner marks 1, 1a as a first layer of the semiconductor substrate 4 and forming the outer marks 2, 2a consisting of the space patterns of the resist as a second layer of the semiconductor substrate 4 on the resist film 3 on the semiconductor substrate 4. The relative positions of the respective marks on the inner side and the outer side are detected by electric signal waveforms, by which the misalignment of the semiconductor substrate 4 and the resist patterns in an x-y direction is measured.

公开(公告)号：JPH11307426A

公开(公告)日：1999-11-05

申请号：JP11216798

申请日：1998-04-22

Applicant: TOSHIBA CORP

Inventor： KUJI TATSUAKI ,  TAKAHATA KAZUHIRO ,  USUI SATOSHI ,  HASHIMOTO KOJI

IPC: H01L21/027 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70

Abstract: PROBLEM TO BE SOLVED: To solve a difference in the effect of reflection by an underlayer material and a difference in size caused by the depth and the taper angle of etching at the same time, by providing a correction means arranged near a light source and capable of simply correcting a pattern on an exposing mask with high accuracy according to the underlayer material. SOLUTION: A gate electrode is formed on the device region of a silicon substrate and two contact holes are formed at the gate electrode and at a device region through an interlayer film. Since the reflection of light used for exposure is larger in the gate electrode made of Wsi than in the device region made of Si, the amount of exposing light absorbed by a resist film used in a lithography process of the contact hole becomes large, and to correct this, the side of a square pattern 2 on the mask is smaller than that of a square pattern 3. When the contact hole is formed, a difference in the amount of exposing light absorbed by the resist film which is caused by the difference between underlayer materials can be corrected by the size of the mask pattern for exposure in this manner.