公开(公告)号：US20230244919A1

公开(公告)日：2023-08-03

申请号：US18097651

申请日：2023-01-17

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Xiangpeng LIANG ,  Ya?nan ZHONG ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: At least one embodiment of the present disclosure provides a reservoir computing apparatus and a data processing method. The reservoir computing apparatus includes: a signal input circuit, configured to receive an input signal; a reservoir circuit, including a plurality of reservoir sub-circuits, in which each reservoir sub-circuit includes a mask sub-circuit and a rotating neuron sub-circuit, the mask sub-circuit is configured to perform a first processing on the input signal with a first weight to obtain a first processing result, and the rotating neuron sub-circuit is configured to perform a second processing on the first processing result to obtain a second processing result; and an output layer circuit, configured to multiply a plurality of second processing results by a second weight matrix to obtain a third processing result. The reservoir computing apparatus optimizes operation efficiency and reduces implementation costs.

公开(公告)号：US20250095728A1

公开(公告)日：2025-03-20

申请号：US18580872

申请日：2021-12-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Huaqiang WU ,  Jianshi TANG ,  He QIAN

IPC: G11C13/00

Abstract: A computing apparatus and a robustness processing method thereof. The robustness processing method includes: based on model parameters of a target algorithm model, obtaining a mapping relationship between the model parameters and the first computing memristor array; based on an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.

公开(公告)号：US20220277866A1

公开(公告)日：2022-09-01

申请号：US17747906

申请日：2022-05-18

Applicant: Tsinghua University ,  Tencent Technology (Shenzhen) Company Limited

Inventor： Jianshi TANG ,  Zhenxuan ZHAO ,  Yuan DAI ,  Wangwei LEE ,  Zhengyou ZHANG ,  Jian YUAN ,  Huaqiang WU ,  He QIAN ,  Bin GAO

IPC: H01B1/24 ,  C08K3/04 ,  C09D5/24 ,  C09D7/61 ,  C09D7/40 ,  C09D175/04

Abstract: This application discloses a conductive paste, a preparation method thereof, and a preparation method of a conductive film using the conductive paste. The conductive paste comprises: a thermoplastic polyurethane, conductive particles, and an organic solvent, the thermoplastic polyurethane and the conductive particles being proportionally mixed in the organic solvent, and the thermoplastic polyurethane being dispersed in the form of particles among the conductive particles. A thermoplastic polyurethane elastomer is used as a binder, and the conductive particles are mixed in the organic solvent containing the thermoplastic polyurethane elastomer. The conductive particles ensure the conductivity of the conductive film prepared using the conductive paste. The thermoplastic polyurethane has strong adhesion ability, and is suitable for use on the surface of most substrates, to form a conductive film with good adhesion and no cracking.

公开(公告)号：US20220137941A1

公开(公告)日：2022-05-05

申请号：US17517096

申请日：2021-11-02

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Ruihua YU ,  Yilong GUO ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G06F8/41 ,  G06N3/10 ,  G06F17/16

Abstract: A compilation method, a compilation apparatus suitable for an In-Memory Computing apparatus, a computing device and a storage medium. The compilation method includes: acquiring calculation information of an algorithm to be compiled; converting the algorithm to be compiled into the first intermediate representation according to the calculation information; mapping the first intermediate representation to the second intermediate representation; and compiling the algorithm to be compiled into instruction information recognized by the In-Memory Computing apparatus according to the hardware information, to make the In-Memory Computing apparatus execute the instruction information. The compilation method may compile the calculation information into instructions that may be directly executed by the In-Memory Computing apparatus, so as to realize the effect of accelerating the operations of various algorithms by using the In-Memory Computing apparatus.

公开(公告)号：US20250078924A1

公开(公告)日：2025-03-06

申请号：US18726931

申请日：2022-01-11

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Han ZHAO ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G11C13/00 ,  G06F17/16

Abstract: At least one embodiment of the present disclosure provides a data processing method based on a memristor array and an electronic apparatus. The data processing method includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array; and inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array, respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively.

公开(公告)号：US20230004357A1

公开(公告)日：2023-01-05

申请号：US17779834

申请日：2020-11-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Bohan LIN ,  Bin GAO ,  Jianshi TANG ,  He QIAN

IPC: G06F7/58

Abstract: A method for generating a random number and a random number generator are provided. The method for generating a random number includes: performing n writing operations on at least one analog resistive random access memory, where each of the n writing operations includes applying at least one writing operation pulse to change a conductance value of an operated analog resistive access memory; and generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations, where n is a positive integer. The method for generating a random number generates random numbers based on the analog characteristics of the analog resistive random access memory, the generated random number does not need back-end correction, and have both high speed and high reliability.

公开(公告)号：US20220335278A1

公开(公告)日：2022-10-20

申请号：US17049348

申请日：2020-01-10

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Peng YAO ,  Bin GAO ,  He QIAN

IPC: G06N3/063 ,  G06F9/345 ,  G06F9/38 ,  G06F9/30

Abstract: Disclosed are a parallel acceleration method for a memristor-based neural network, a parallel acceleration processor based on a memristor-based neural network and a parallel acceleration device based on a memristor-based neural network. The neural network includes a plurality of functional layers sequentially provided, wherein the plurality of functional layers include a first functional layer and a second functional layer following the first functional layer, the first functional layer includes a plurality of first memristor arrays in parallel, and the plurality of first memristor arrays are configured to execute an operation of the first functional layer in parallel and to output a result of the operation to the second functional layer. The parallel acceleration method includes: executing the operation of the first functional layer in parallel via the plurality of first memristor arrays and outputting the result of the operation to the second functional layer.

公开(公告)号：US20250005353A1

公开(公告)日：2025-01-02

申请号：US18695316

申请日：2021-12-28

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Ruihua YU ,  Peng YAO ,  Dabin WU ,  Bin GAO ,  Hu HE ,  Jianshi TANG ,  He QIAN

IPC: G06N3/08

Abstract: A data processing apparatus and a data processing method. The data processing apparatus includes: a bidirectional data processing module, including at least one storage and computing integration computing array; a controlling module, configured to switch a working mode of the bidirectional data processing module to an inference working mode to perform an inference computing task, and to switch the working mode of the bidirectional data processing module to a training working mode to perform a training computing task; a parameter management module, configured to set a weight parameter of the bidirectional data processing module; and an inputting and outputting module, configured to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing module and generate outputting data according to the computing outputting signal.

公开(公告)号：US20240170060A1

公开(公告)日：2024-05-23

申请号：US17788408

申请日：2021-12-14

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79

Abstract: A data processing method based on a memristor array and an electronic apparatus are disclosed. The data processing method based on a memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array; inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.

公开(公告)号：US20230168891A1

公开(公告)日：2023-06-01

申请号：US17780327

申请日：2021-11-05

Applicant: TSINGHUA UNIVERSITY

Inventor： Peng YAO ,  Bin GAO ,  Dabin WU ,  Hu HE ,  Jianshi TANG ,  He QIAN ,  Huaqiang WU

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/4881 ,  G06F9/3877

Abstract: An in-memory computing processor, an in-memory computing processing system, an in-memory computing processing apparatus, and a deployment method of an algorithm model based on the in-memory computing processor are disclosed. The in-memory computing processor includes a first master control unit and a plurality of memristor processing modules, and the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules, the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate.