公开(公告)号：US20250005353A1

公开(公告)日：2025-01-02

申请号：US18695316

申请日：2021-12-28

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Ruihua YU ,  Peng YAO ,  Dabin WU ,  Bin GAO ,  Hu HE ,  Jianshi TANG ,  He QIAN

IPC: G06N3/08

Abstract: A data processing apparatus and a data processing method. The data processing apparatus includes: a bidirectional data processing module, including at least one storage and computing integration computing array; a controlling module, configured to switch a working mode of the bidirectional data processing module to an inference working mode to perform an inference computing task, and to switch the working mode of the bidirectional data processing module to a training working mode to perform a training computing task; a parameter management module, configured to set a weight parameter of the bidirectional data processing module; and an inputting and outputting module, configured to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing module and generate outputting data according to the computing outputting signal.

公开(公告)号：US20230168891A1

公开(公告)日：2023-06-01

申请号：US17780327

申请日：2021-11-05

Applicant: TSINGHUA UNIVERSITY

Inventor： Peng YAO ,  Bin GAO ,  Dabin WU ,  Hu HE ,  Jianshi TANG ,  He QIAN ,  Huaqiang WU

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/4881 ,  G06F9/3877

Abstract: An in-memory computing processor, an in-memory computing processing system, an in-memory computing processing apparatus, and a deployment method of an algorithm model based on the in-memory computing processor are disclosed. The in-memory computing processor includes a first master control unit and a plurality of memristor processing modules, and the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules, the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate.