公开(公告)号：US20240320083A1

公开(公告)日：2024-09-26

申请号：US18574247

申请日：2021-12-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Huaqiang WU ,  Jianshi TANG ,  He QIAN

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073

Abstract: A storage and computation integrated apparatus and a calibration method therefor. The storage and computation integrated apparatus includes a first processing unit, which includes: a first computation memristor array; a first calibration memristor array; and a first processing unit. The calibration method includes: determining, by means of off-chip training, a first computation weight matrix which corresponds to a first computation memristor array, and writing the first computation weight matrix into the first computation memristor array; and on the basis of the first computation memristor array where the first computation weight matrix has been written and the first computation weight matrix, performing on-chip training on a first calibration memristor array, so as to adjust a weight value of the first calibration memristor array.

公开(公告)号：US20220374688A1

公开(公告)日：2022-11-24

申请号：US17049349

申请日：2020-03-06

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Peng YAO ,  Bin GAO ,  Qingtian ZHANG ,  He QIAN

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A training method and a training device for a neural network based on memristors are provided. The neural network includes a plurality of neuron layers connected one by one and weight parameters between the plurality of neuron layers, and the training method includes: training the weight parameters of the neural network, and programming a memristor array based on the weight parameters after being trained to write the weight parameters after being trained into the memristor array; and updating a critical layer or several critical layers of the weight parameters of the neural network by adjusting conductance values of at least part of memristors of the memristor array.

公开(公告)号：US20250005353A1

公开(公告)日：2025-01-02

申请号：US18695316

申请日：2021-12-28

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Ruihua YU ,  Peng YAO ,  Dabin WU ,  Bin GAO ,  Hu HE ,  Jianshi TANG ,  He QIAN

IPC: G06N3/08

Abstract: A data processing apparatus and a data processing method. The data processing apparatus includes: a bidirectional data processing module, including at least one storage and computing integration computing array; a controlling module, configured to switch a working mode of the bidirectional data processing module to an inference working mode to perform an inference computing task, and to switch the working mode of the bidirectional data processing module to a training working mode to perform a training computing task; a parameter management module, configured to set a weight parameter of the bidirectional data processing module; and an inputting and outputting module, configured to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing module and generate outputting data according to the computing outputting signal.

公开(公告)号：US20230168891A1

公开(公告)日：2023-06-01

申请号：US17780327

申请日：2021-11-05

Applicant: TSINGHUA UNIVERSITY

Inventor： Peng YAO ,  Bin GAO ,  Dabin WU ,  Hu HE ,  Jianshi TANG ,  He QIAN ,  Huaqiang WU

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/4881 ,  G06F9/3877

Abstract: An in-memory computing processor, an in-memory computing processing system, an in-memory computing processing apparatus, and a deployment method of an algorithm model based on the in-memory computing processor are disclosed. The in-memory computing processor includes a first master control unit and a plurality of memristor processing modules, and the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules, the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate.

公开(公告)号：US20220277199A1

公开(公告)日：2022-09-01

申请号：US17750052

申请日：2022-05-20

Applicant: Huawei Technologies Co., Ltd. ,  TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Kanwen WANG ,  Jianxing LIAO ,  Tieying WANG ,  Huaqiang WU

IPC: G06N3/08 ,  G06N3/04

Abstract: A method for data processing in a neural network system and a neural network system are provided. The method includes: inputting training data into a neural network system to obtain first output data, and adjusting, based on a deviation between the first output data and target output data, a weight value stored in at least one in-memory computing unit in some neural network arrays in a plurality of neural network arrays in the neural network system using parallel acceleration. The some neural network arrays are configured to implement computing of some neural network layers in the neural network system. The method may improve performance and recognition accuracy of the neural network system.

公开(公告)号：US20250095728A1

公开(公告)日：2025-03-20

申请号：US18580872

申请日：2021-12-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Huaqiang WU ,  Jianshi TANG ,  He QIAN

IPC: G11C13/00

Abstract: A computing apparatus and a robustness processing method thereof. The robustness processing method includes: based on model parameters of a target algorithm model, obtaining a mapping relationship between the model parameters and the first computing memristor array; based on an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.

公开(公告)号：US20220335278A1

公开(公告)日：2022-10-20

申请号：US17049348

申请日：2020-01-10

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Peng YAO ,  Bin GAO ,  He QIAN

IPC: G06N3/063 ,  G06F9/345 ,  G06F9/38 ,  G06F9/30

Abstract: Disclosed are a parallel acceleration method for a memristor-based neural network, a parallel acceleration processor based on a memristor-based neural network and a parallel acceleration device based on a memristor-based neural network. The neural network includes a plurality of functional layers sequentially provided, wherein the plurality of functional layers include a first functional layer and a second functional layer following the first functional layer, the first functional layer includes a plurality of first memristor arrays in parallel, and the plurality of first memristor arrays are configured to execute an operation of the first functional layer in parallel and to output a result of the operation to the second functional layer. The parallel acceleration method includes: executing the operation of the first functional layer in parallel via the plurality of first memristor arrays and outputting the result of the operation to the second functional layer.