公开(公告)号：US20230244919A1

公开(公告)日：2023-08-03

申请号：US18097651

申请日：2023-01-17

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Xiangpeng LIANG ,  Ya?nan ZHONG ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: At least one embodiment of the present disclosure provides a reservoir computing apparatus and a data processing method. The reservoir computing apparatus includes: a signal input circuit, configured to receive an input signal; a reservoir circuit, including a plurality of reservoir sub-circuits, in which each reservoir sub-circuit includes a mask sub-circuit and a rotating neuron sub-circuit, the mask sub-circuit is configured to perform a first processing on the input signal with a first weight to obtain a first processing result, and the rotating neuron sub-circuit is configured to perform a second processing on the first processing result to obtain a second processing result; and an output layer circuit, configured to multiply a plurality of second processing results by a second weight matrix to obtain a third processing result. The reservoir computing apparatus optimizes operation efficiency and reduces implementation costs.

公开(公告)号：US20250005353A1

公开(公告)日：2025-01-02

申请号：US18695316

申请日：2021-12-28

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Ruihua YU ,  Peng YAO ,  Dabin WU ,  Bin GAO ,  Hu HE ,  Jianshi TANG ,  He QIAN

IPC: G06N3/08

Abstract: A data processing apparatus and a data processing method. The data processing apparatus includes: a bidirectional data processing module, including at least one storage and computing integration computing array; a controlling module, configured to switch a working mode of the bidirectional data processing module to an inference working mode to perform an inference computing task, and to switch the working mode of the bidirectional data processing module to a training working mode to perform a training computing task; a parameter management module, configured to set a weight parameter of the bidirectional data processing module; and an inputting and outputting module, configured to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing module and generate outputting data according to the computing outputting signal.

公开(公告)号：US20240170060A1

公开(公告)日：2024-05-23

申请号：US17788408

申请日：2021-12-14

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79

Abstract: A data processing method based on a memristor array and an electronic apparatus are disclosed. The data processing method based on a memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array; inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.

公开(公告)号：US20230168891A1

公开(公告)日：2023-06-01

申请号：US17780327

申请日：2021-11-05

Applicant: TSINGHUA UNIVERSITY

Inventor： Peng YAO ,  Bin GAO ,  Dabin WU ,  Hu HE ,  Jianshi TANG ,  He QIAN ,  Huaqiang WU

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/4881 ,  G06F9/3877

Abstract: An in-memory computing processor, an in-memory computing processing system, an in-memory computing processing apparatus, and a deployment method of an algorithm model based on the in-memory computing processor are disclosed. The in-memory computing processor includes a first master control unit and a plurality of memristor processing modules, and the first master control unit is configured to be capable of dispatching and controlling the plurality of memristor processing modules, the plurality of memristor processing modules are configured to be capable of calculating under the dispatch and control of the first master control unit, and the plurality of memristor processing modules are further configured to be capable of communicating independently of the first master control unit to calculate.

公开(公告)号：US20220275220A1

公开(公告)日：2022-09-01

申请号：US17747911

申请日：2022-05-18

Applicant: Tsinghua University ,  Tencent Technology (Shenzhen) Company Limited

Inventor： Jianshi TANG ,  Zhenxuan ZHAO ,  Yuan DAI ,  Zhengyou ZHANG ,  Jian YUAN ,  Huaqiang WU ,  He QIAN ,  Bin GAO

IPC: C09D5/24 ,  C09D7/61 ,  C09D7/20 ,  C09D175/04 ,  C09D163/00 ,  H01C10/10 ,  H01C17/00 ,  B25J9/16

Abstract: Embodiments of this application provide a method for preparing a thin film piezoresistive material, a thin film piezoresistive material, a robot, and a device. The method includes: determining a mass ratio of conductive particles to a cross-linked polymer in preparation of the thin film piezoresistive material, a value range of the mass ratio being 3:97 to 20:80; dispersing the conductive particles and the cross-linked polymer in a solvent according to the mass ratio, to obtain a first dispersion; and curing the first dispersion by using a liquid dropping method within a temperature range of 25° C. to 200° C., to obtain the thin film piezoresistive material. The technical solutions provided by the embodiments of this application provide a method for preparing a thin film piezoresistive material through liquid dropping, thereby effectively controlling the thickness of the piezoresistive material, so that the prepared thin film piezoresistive material has a relatively small thickness.

公开(公告)号：US20240320083A1

公开(公告)日：2024-09-26

申请号：US18574247

申请日：2021-12-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Huaqiang WU ,  Jianshi TANG ,  He QIAN

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073

Abstract: A storage and computation integrated apparatus and a calibration method therefor. The storage and computation integrated apparatus includes a first processing unit, which includes: a first computation memristor array; a first calibration memristor array; and a first processing unit. The calibration method includes: determining, by means of off-chip training, a first computation weight matrix which corresponds to a first computation memristor array, and writing the first computation weight matrix into the first computation memristor array; and on the basis of the first computation memristor array where the first computation weight matrix has been written and the first computation weight matrix, performing on-chip training on a first calibration memristor array, so as to adjust a weight value of the first calibration memristor array.

公开(公告)号：US20220374688A1

公开(公告)日：2022-11-24

申请号：US17049349

申请日：2020-03-06

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Peng YAO ,  Bin GAO ,  Qingtian ZHANG ,  He QIAN

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A training method and a training device for a neural network based on memristors are provided. The neural network includes a plurality of neuron layers connected one by one and weight parameters between the plurality of neuron layers, and the training method includes: training the weight parameters of the neural network, and programming a memristor array based on the weight parameters after being trained to write the weight parameters after being trained into the memristor array; and updating a critical layer or several critical layers of the weight parameters of the neural network by adjusting conductance values of at least part of memristors of the memristor array.

公开(公告)号：US20220061729A1

公开(公告)日：2022-03-03

申请号：US17412016

申请日：2021-08-25

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: A61B5/304 ,  G11C13/00 ,  A61B5/31 ,  A61B5/00

Abstract: A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.

公开(公告)号：US20210184025A1

公开(公告)日：2021-06-17

申请号：US17058211

申请日：2018-08-03

Applicant: TSINGHUA UNIVERSITY

Inventor： Feng XU ,  Bin GAO ,  Xinyi LI ,  Huaqiang WU ,  He QIAN

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.

公开(公告)号：US20250078924A1

公开(公告)日：2025-03-06

申请号：US18726931

申请日：2022-01-11

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Han ZHAO ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: G11C13/00 ,  G06F17/16

Abstract: At least one embodiment of the present disclosure provides a data processing method based on a memristor array and an electronic apparatus. The data processing method includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array; and inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array, respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively.