公开(公告)号：US08736033B1

公开(公告)日：2014-05-27

申请号：US13798116

申请日：2013-03-13

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chen Chuo ,  Wei-Ming Cheng

IPC: H01L23/60

CPC classification number: H01L24/19 ,  H01L23/552 ,  H01L2224/04105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0715

Abstract: An embedded-electronic-device package includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer, a shielding-metal layer and conductive vias. The core layer includes a first surface, a second surface opposite to the second surface and a cavity penetrating the core layer. The electronic device is disposed in the cavity including an inner surface. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers part of the electronic device. The second dielectric layer disposed on the second surface is filled in rest of the cavity, covers rest of the electronic device. The first and second dielectric layers cover the electronic device. The shielding-metal layer covers the inner surface. The conductive vias are respectively disposed in the first and second dielectric layers and extended respectively from outer surfaces of the first and second dielectric layers to the shielding-metal layer.

Abstract translation: 嵌入式电子器件封装包括芯层，电子器件，第一介电层，第二介电层，屏蔽金属层和导电通孔。 芯层包括第一表面，与第二表面相对的第二表面和穿透核心层的空腔。 电子设备设置在包括内表面的空腔中。 布置在第一表面上的第一介电层填充在空腔的一部分中并覆盖电子设备的一部分。 设置在第二表面上的第二介电层填充在空腔的其余部分中，覆盖电子设备的其余部分。 第一和第二电介质层覆盖电子器件。 屏蔽金属层覆盖内表面。 导电通孔分别设置在第一和第二电介质层中，分别从第一和第二电介质层的外表面延伸到屏蔽金属层。

公开(公告)号：US20140225272A1

公开(公告)日：2014-08-14

申请号：US13762385

申请日：2013-02-08

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Yu-Chen Chuo ,  Wei-Ming Cheng

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/82039 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/00

Abstract: An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.

Abstract translation: 嵌入式电子器件封装结构包括芯层，电子器件，第一介电层，第二介电层和导电通孔。 芯层具有空腔，与第一表面相对的第一表面和第二表面。 电子设备设置在空腔中。 设置在第一表面上的第一介电层填充在空腔的一部分中并且覆盖电子设备的一侧。 设置在第二表面上的第二电介质层填充在空腔中，覆盖电子器件的另一侧并连接第一电介质层。 第一和第二介电层完全覆盖电子设备。 导电通孔围绕电子器件的周围设置并穿透第一和第二介电层和芯层。 导电通孔分别连接第一和第二介电层。

公开(公告)号：US08803310B1

公开(公告)日：2014-08-12

申请号：US13762385

申请日：2013-02-08

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chen Chuo ,  Wei-Ming Cheng

IPC: H01L23/12

CPC classification number: H01L23/552 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/82039 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/00

Abstract: An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.

Abstract translation: 嵌入式电子器件封装结构包括芯层，电子器件，第一介电层，第二介电层和导电通孔。 芯层具有空腔，与第一表面相对的第一表面和第二表面。 电子设备设置在空腔中。 设置在第一表面上的第一介电层填充在空腔的一部分中并且覆盖电子设备的一侧。 设置在第二表面上的第二电介质层填充在空腔中，覆盖电子器件的另一侧并连接第一电介质层。 第一和第二介电层完全覆盖电子设备。 导电通孔围绕电子器件的周围设置并穿透第一和第二介电层和芯层。 导电通孔分别连接第一和第二介电层。