公开(公告)号：US11201123B2

公开(公告)日：2021-12-14

申请号：US16673967

申请日：2019-11-05

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hsien Chien ,  Po-Chen Lin ,  Wen-Liang Yeh ,  Chien-Chou Chen

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01Q1/24

Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 μm to 10 μm.

公开(公告)号：US10797017B2

公开(公告)日：2020-10-06

申请号：US16283657

申请日：2019-02-22

Applicant: Unimicron Technology Corp.

Inventor： Po-Chen Lin ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Chien-Chou Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/52

Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

公开(公告)号：US20190295984A1

公开(公告)日：2019-09-26

申请号：US16283657

申请日：2019-02-22

Applicant: Unimicron Technology Corp.

Inventor： Po-Chen Lin ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Chien-Chou Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/52

Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.