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公开(公告)号：US11201123B2
公开(公告)日：2021-12-14
申请号：US16673967
申请日：2019-11-05
Applicant: Unimicron Technology Corp.
Inventor： Chun-Hsien Chien , Po-Chen Lin , Wen-Liang Yeh , Chien-Chou Chen
Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 μm to 10 μm.
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公开(公告)号：US11348869B2
公开(公告)日：2022-05-31
申请号：US17100932
申请日：2020-11-22
Applicant: Unimicron Technology Corp.
Inventor： Chien-Chou Chen , Chun-Hsien Chien , Wen-Liang Yeh , Wei-Ti Lin
IPC: H01L23/04 , H01L23/522 , H01L23/00 , H01L21/50
Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
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公开(公告)号：US10660202B1
公开(公告)日：2020-05-19
申请号：US16221587
申请日：2018-12-17
Applicant: Unimicron Technology Corp.
Inventor： Wen-Liang Yeh , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
IPC: H05K1/00 , H05K1/02 , H05K1/03 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/02 , H05K3/10 , H05K3/30 , H05K3/46 , H05K3/28 , H05K3/34
Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
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公开(公告)号：US11678441B2
公开(公告)日：2023-06-13
申请号：US16950910
申请日：2020-11-18
Applicant: Unimicron Technology Corp.
Inventor： Wei-Ti Lin , Chun-Hsien Chien , Chien-Chou Chen , Fu-Yang Chen , Ra-Min Tain
CPC classification number: H05K3/4644 , H05K1/111 , H05K1/115 , H05K1/181 , H05K3/007 , H05K3/0097 , H05K3/28 , H05K3/303 , H05K3/4007 , H05K3/421 , H05K3/429 , H05K2201/09136 , H05K2201/09509 , H05K2201/09827 , H05K2201/10234 , H05K2201/10522
Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
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公开(公告)号：US20200163215A1
公开(公告)日：2020-05-21
申请号：US16221587
申请日：2018-12-17
Applicant: Unimicron Technology Corp.
Inventor： Wen-Liang Yeh , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
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Patent Agency Ranking
公开(公告)号：US20200075711A1
公开(公告)日：2020-03-05
申请号：US16159726
申请日：2018-10-15
Applicant: Unimicron Technology Corp.
Inventor： Yu-Hua Chen , Fu-Yang Chen , Chun-Hsien Chien , Chien-Chou Chen , Wei-Ti Lin
IPC: H01L49/02 , H01L23/522 , H01L23/532 , H01L23/15 , H01L23/498
Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
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公开(公告)号：US10863618B2
公开(公告)日：2020-12-08
申请号：US16283670
申请日：2019-02-22
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Pei-Wei Wang , Bo-Cheng Lin , Chun-Hsien Chien , Chien-Chou Chen
IPC: H05K1/02 , H05K1/11 , H05K3/30 , H05K3/46 , H01Q3/38 , H01Q1/24 , H01Q1/38 , H05K3/02 , H05K3/40 , H05K1/18
Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.
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公开(公告)号：US10797017B2
公开(公告)日：2020-10-06
申请号：US16283657
申请日：2019-02-22
Applicant: Unimicron Technology Corp.
Inventor： Po-Chen Lin , Ra-Min Tain , Chun-Hsien Chien , Chien-Chou Chen
Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.
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公开(公告)号：US20200161518A1
公开(公告)日：2020-05-21
申请号：US16281108
申请日：2019-02-21
Applicant: Unimicron Technology Corp.
Inventor： Yi-Cheng Lin , Yu-Hua Chen , Chun-Hsien Chien , Chien-Chou Chen , Cheng-Hui Wu
IPC: H01L33/62 , H01L33/52 , H01L23/498 , H01L23/538 , H01L23/31
Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
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10.发明申请公开(公告)号：US20190295984A1
公开(公告)日：2019-09-26
申请号：US16283657
申请日：2019-02-22
Applicant: Unimicron Technology Corp.
Inventor： Po-Chen Lin , Ra-Min Tain , Chun-Hsien Chien , Chien-Chou Chen
Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.
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