公开(公告)号：US20250038055A1

公开(公告)日：2025-01-30

申请号：US18358616

申请日：2023-07-25

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/495

Abstract: Semiconductor packages are provided. In one example, a semiconductor package includes a submount. The semiconductor package further includes a semiconductor die on the submount. The submount defines a base plane, and the submount includes at least one stud protrusion extending from the base plane in a direction toward the semiconductor die.

公开(公告)号：US20240421029A1

公开(公告)日：2024-12-19

申请号：US18336358

申请日：2023-06-16

Applicant: Wolfspeed, Inc.

Inventor： Devarajan Balaraman ,  Daniel Ginn Richter

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L29/66 ,  H01L29/872

Abstract: Semiconductor packages are provided. In one example, a semiconductor package includes a submount having a first surface and a second surface opposing the first surface. The semiconductor package includes at least one semiconductor die attached to the second surface of submount. The semiconductor package includes an insulating portion on the second surface of the submount and on the at least one semiconductor die. The insulating portion forms a first external surface of the semiconductor package. The semiconductor package includes at least one through-mold via extending from the first external surface through the insulating portion to at least one of the semiconductor die or the submount.

公开(公告)号：US20240258217A1

公开(公告)日：2024-08-01

申请号：US18161144

申请日：2023-01-30

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49582 ,  H01L21/4821 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L23/293 ,  H01L23/296 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/73265 ,  H01L2924/10272

Abstract: A semiconductor device package includes a conductive submount, a metal layer comprising a first material on the conductive submount, and at least one conductive buffer layer comprising a second material on the metal layer. The conductive buffer layer may be between the metal layer and the conductive submount, or may be between the metal layer and a transistor die on the conductive submount. The second material of the conductive buffer layer has limited or no solid solubility with respect to the first material of the metal layer. Related packages and fabrication techniques are also discussed.

公开(公告)号：US20240182757A1

公开(公告)日：2024-06-06

申请号：US18074079

申请日：2022-12-02

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman

IPC: C09J9/02 ,  C09J1/00 ,  H01L23/00

CPC classification number: C09J9/02 ,  C09J1/00 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29324 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29457 ,  H01L2224/29464 ,  H01L2224/2948 ,  H01L2224/29484 ,  H01L2224/32225 ,  H01L2224/32503

Abstract: Die-attach materials are provided. In one example, the die-attach material may include a plurality of core-shell particles. Each core-shell particle may include a core and a shell on the core. The core may include a conducting material. The shell may include an alloy. The alloy may include a first element and a second element. The second element may segregate into one or more grain boundaries in the die-attach material during bonding of the die-attach material.

公开(公告)号：US20240243031A1

公开(公告)日：2024-07-18

申请号：US18154353

申请日：2023-01-13

Applicant: Wolfspeed, Inc.

Inventor： Yusheng Lin ,  Kuldeep Saxena ,  Devarajan Balaraman

IPC: H01L23/373 ,  H01L23/538 ,  H01L25/07 ,  H01L29/16 ,  H01L29/872

CPC classification number: H01L23/3735 ,  H01L23/5389 ,  H01L25/072 ,  H01L29/1608 ,  H01L29/872

Abstract: Power semiconductor packages are provided. In one example, a power semiconductor package may include a first carrier substrate. The first carrier substrate may include one or more conductive pads. The power semiconductor package may include a second carrier substrate. The second carrier substrate may include one or more conductive leads. The power semiconductor package may include a power semiconductor die having a first surface and an opposing second surface. The first surface of the power semiconductor die may be directly coupled to the first carrier substrate. The second surface of the power semiconductor die may be directly coupled to the second carrier substrate.

公开(公告)号：US20250122413A1

公开(公告)日：2025-04-17

申请号：US18487665

申请日：2023-10-16

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman ,  Kuldeep Saxena

IPC: C09J179/08 ,  C09J9/02 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/495

Abstract: Semiconductor device packages are provided. In one example, a semiconductor device package comprises a first structure having a first surface in the semiconductor device package, a second structure having a second surface in the semiconductor device package, and an adhesion promoting layer in contact with the first surface on a first side and the second surface on a second side. The adhesion promoting layer comprises a polyimide containing repeating units derived from a tetracarboxylic dianhydride and at least one diamine containing a functional group.

公开(公告)号：US12224218B2

公开(公告)日：2025-02-11

申请号：US17670174

申请日：2022-02-11

Applicant: Wolfspeed, Inc.

Inventor： Geza Dezsi ,  Devarajan Balaraman ,  Brice McPherson

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L29/16 ,  H01L29/78 ,  H01L29/872

Abstract: Semiconductor packages and, more particularly, semiconductor packages with increased power handling capabilities are disclosed. Semiconductor packages may include lead frame structures and corresponding housings that incorporate semiconductor die. To promote increased current and voltage capabilities, exemplary semiconductor packages include one or more arrangements of creepage extension structures, lead frame structures that may include integral thermal pads, additional thermal elements, and combinations thereof. Creepage extension structures may be arranged as part of top sides of semiconductor packages along with thermal pads of lead frame structures and additional thermal elements. Creepage extension structures may also be arranged as part of top sides and along on one or more peripheral edges of semiconductor packages to promote further increases in power handling.

公开(公告)号：USD1056862S1

公开(公告)日：2025-01-07

申请号：US29866001

申请日：2022-08-24

Applicant: Wolfspeed, Inc.

Designer： Geza Dezsi ,  Devarajan Balaraman ,  Brice McPherson

公开(公告)号：US20240282741A1

公开(公告)日：2024-08-22

申请号：US18169518

申请日：2023-02-15

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/29 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/2979 ,  H01L2224/29847 ,  H01L2224/29987 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2924/182

Abstract: Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

公开(公告)号：US20250149432A1

公开(公告)日：2025-05-08

申请号：US19013061

申请日：2025-01-08

Applicant: Wolfspeed, Inc.

Inventor： Sayan Seal ,  Kuldeep Saxena ,  Devarajan Balaraman

IPC: H01L23/498 ,  H01L23/31

Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer