公开(公告)号：USD969762S1

公开(公告)日：2022-11-15

申请号：US29811014

申请日：2021-10-11

Applicant: Wolfspeed, Inc.

Designer： Kuldeep Saxena

公开(公告)号：US20250122413A1

公开(公告)日：2025-04-17

申请号：US18487665

申请日：2023-10-16

Applicant: Wolfspeed, Inc.

Inventor： Afshin Dadvand ,  Devarajan Balaraman ,  Kuldeep Saxena

IPC: C09J179/08 ,  C09J9/02 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/495

Abstract: Semiconductor device packages are provided. In one example, a semiconductor device package comprises a first structure having a first surface in the semiconductor device package, a second structure having a second surface in the semiconductor device package, and an adhesion promoting layer in contact with the first surface on a first side and the second surface on a second side. The adhesion promoting layer comprises a polyimide containing repeating units derived from a tetracarboxylic dianhydride and at least one diamine containing a functional group.

公开(公告)号：US12199045B2

公开(公告)日：2025-01-14

申请号：US16832918

申请日：2020-03-27

Applicant: Wolfspeed, Inc.

Inventor： Guy Moxey ,  Kuldeep Saxena

IPC: H01L23/538 ,  H01L23/495 ,  H01L23/522

Abstract: A power semiconductor package includes a power semiconductor die, a housing, a first lead, and a second lead. The housing includes a top side and a bottom side. The first lead is in contact with a first electrical contact of the power semiconductor die. Further, the first lead includes a heat exchanging portion on the top side of the housing and an electrical contact portion on the bottom side of the housing. At least 7.5 mm2 of the electrical contact portion of the first lead is available for contacting a printed circuit board. The second lead is in contact with a second electrical contact of the power semiconductor die. The second lead includes a heat exchanging portion on the bottom side of the housing and an electrical contact portion also on the bottom side of the housing.

公开(公告)号：US20240304507A1

公开(公告)日：2024-09-12

申请号：US18179036

申请日：2023-03-06

Applicant: Wolfspeed, Inc.

Inventor： Geza Dezsi ,  Yusheng Lin ,  Kuldeep Saxena

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/3107 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/49111 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/13091

Abstract: Power semiconductor packages are provided. In one example, a power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount type (SMT) connection structures on the second side.

公开(公告)号：US20240243031A1

公开(公告)日：2024-07-18

申请号：US18154353

申请日：2023-01-13

Applicant: Wolfspeed, Inc.

Inventor： Yusheng Lin ,  Kuldeep Saxena ,  Devarajan Balaraman

IPC: H01L23/373 ,  H01L23/538 ,  H01L25/07 ,  H01L29/16 ,  H01L29/872

CPC classification number: H01L23/3735 ,  H01L23/5389 ,  H01L25/072 ,  H01L29/1608 ,  H01L29/872

Abstract: Power semiconductor packages are provided. In one example, a power semiconductor package may include a first carrier substrate. The first carrier substrate may include one or more conductive pads. The power semiconductor package may include a second carrier substrate. The second carrier substrate may include one or more conductive leads. The power semiconductor package may include a power semiconductor die having a first surface and an opposing second surface. The first surface of the power semiconductor die may be directly coupled to the first carrier substrate. The second surface of the power semiconductor die may be directly coupled to the second carrier substrate.

公开(公告)号：US20230420329A1

公开(公告)日：2023-12-28

申请号：US17849316

申请日：2022-06-24

Applicant: Wolfspeed, Inc.

Inventor： Adil Salman ,  Ajay Sekar Chandrasekaran ,  Kuldeep Saxena

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3677 ,  H01L23/3735 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73265

Abstract: Top-side cooled semiconductor packages are disclosed. A top-side cooled semiconductor package may be a leaded or a leadless semiconductor package. A top-side cooled semiconductor package can include built-in electrical isolation for a semiconductor die within a housing of the semiconductor package. A top-side cooled semiconductor package may include one or more arrangements of creepage extension structures. A creepage extension structure may be arranged as part of a top side of a housing, of part of at least one peripheral side of the housing, as part of a bottom side of the housing, or combinations thereof.

公开(公告)号：US20250149432A1

公开(公告)日：2025-05-08

申请号：US19013061

申请日：2025-01-08

Applicant: Wolfspeed, Inc.

Inventor： Sayan Seal ,  Kuldeep Saxena ,  Devarajan Balaraman

IPC: H01L23/498 ,  H01L23/31

Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer

公开(公告)号：US12224233B2

公开(公告)日：2025-02-11

申请号：US17159925

申请日：2021-01-27

Applicant: Wolfspeed, Inc.

Inventor： Sayan Seal ,  Kuldeep Saxena ,  Devarajan Balaraman

IPC: H01L23/498 ,  H01L23/31

Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.