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    RESOLUTION PROGRAMMABLE SAR ADC
    1.
    发明申请
    RESOLUTION PROGRAMMABLE SAR ADC 审中-公开

    公开(公告)号：WO2018164834A1

    公开(公告)日：2018-09-13

    申请号：PCT/US2018/018898

    申请日：2018-02-21

    Applicant: XILINX, INC.

    Inventor： CHO, Junho ,  POON, Chi, Fung ,  UPADHYAYA, Parag

    IPC: H03M1/46 ,  H03M1/40

    Abstract: An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit (202) configured to receive an analog input signal; a digital-to-analog converter (DAC) (203); an adder (204) having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit (206) coupled to an output of the adder and configured to perform a comparison operation; and a control circuit (250), coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.

    LOW POWER INVERTER-BASED CTLE
    2.
    发明申请
    LOW POWER INVERTER-BASED CTLE 审中-公开

    公开(公告)号：WO2021183202A1

    公开(公告)日：2021-09-16

    申请号：PCT/US2020/067191

    申请日：2020-12-28

    Applicant: XILINX, INC.

    Inventor： CHO, Junho ,  ZHENG, Kevin ,  UPADHYAYA, Parag

    IPC: H03K19/017 ,  H03F1/42

    Abstract: Electronic devices that include a continuous time linear equalizer, CTLE, are provided. An example of a CTLE includes a first inverter (402); a second inverter (404) having an input to receive an input signal (IN); a capacitor (408) coupled between an input of the first inverter (402) and the input of the second inverter (404); a resistor (410) coupled between a common-mode voltage (VCM) and the input of the first inverter; a third inverter (406) having an output to provide an output signal (Out); and a node (416) comprising an output of the first inverter (404), an output of the second inverter (402), an input of the third inverter (406), and the output of the third inverter.

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