公开(公告)号：WO2009055129A1

公开(公告)日：2009-04-30

申请号：PCT/US2008/073529

申请日：2008-08-18

Applicant: XILINX, INC.

Inventor： LUO, Yuhao ,  WU, Shuxian ,  WU, Xin X. ,  AHN, Jae-Gyung ,  NAYAK, Deepak Kumar ,  GITLIN, Daniel

IPC: H01L27/02

CPC classification number: H01L27/0251

Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Abstract translation: 公开了一种保护形成在集成电路的管芯上的晶体管的方法。 该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。 还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

公开(公告)号：WO2021108037A1

公开(公告)日：2021-06-03

申请号：PCT/US2020/054891

申请日：2020-10-09

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Xin X. ,  FRANS, Yohan

IPC: H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

公开(公告)号：EP4066281A1

公开(公告)日：2022-10-05

申请号：EP20800413.5

申请日：2020-10-09

Applicant: Xilinx, Inc.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Xin X. ,  FRANS, Yohan

IPC: H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528