公开(公告)号：WO2022265704A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/020477

申请日：2022-03-16

Applicant: XILINX, INC.

Inventor： ZHANG, Wenfeng ,  WU, Zhaoyin Daniel ,  UPADHYAYA, Parag

IPC: H04L25/03 ,  H04L25/06 ,  H04L7/00

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

公开(公告)号：WO2022271254A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/023364

申请日：2022-04-04

Applicant: XILINX, INC.

Inventor： WU, Zhaoyin Daniel ,  UPADHYAYA, Parag ,  SHI, Hong

IPC: H01L23/64 ,  H01F17/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/528 ,  H01L21/60 ,  H01L23/522 ,  H01F17/0006 ,  H01F2017/0073 ,  H01L2223/6638 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/16 ,  H01L25/0655 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01Q1/2283

Abstract: A package device comprises a first transceiver (110) comprising a first integrated circuit (IC) die and transmitter circuitry (112), and a second transceiver (120) comprising a second IC die and receiver circuitry (124). The receiver circuitry is coupled to the transmitter circuitry via a channel (140). The package device further comprises an interconnection device (130) connected to the first IC die and the second IC die. The interconnection device comprises the channel (140) connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element (142) disposed external to the first IC die and the second IC die and along the channel.

公开(公告)号：EP4334977A1

公开(公告)日：2024-03-13

申请号：EP22719440.4

申请日：2022-04-04

Applicant: Xilinx, Inc.

Inventor： WU, Zhaoyin Daniel ,  UPADHYAYA, Parag ,  SHI, Hong

IPC: H01L23/64 ,  H01F17/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/528 ,  H01L21/60 ,  H01L23/522

公开(公告)号：EP4356572A1

公开(公告)日：2024-04-24

申请号：EP22719059.2

申请日：2022-03-16

Applicant: Xilinx, Inc.

Inventor： ZHANG, Wenfeng ,  WU, Zhaoyin Daniel ,  UPADHYAYA, Parag

IPC: H04L25/03 ,  H04L25/06 ,  H04L7/00

CPC classification number: H04L25/03 ,  H04L25/03012 ,  H04L25/06 ,  H04L7/0058