公开(公告)号：WO2021243225A8

公开(公告)日：2021-12-02

申请号：PCT/US2021/034882

申请日：2021-05-28

Applicant: FORMFACTOR, INC.

Inventor： HENSON, Roy J. ,  POWELL, Shawn O.

IPC: H01L21/04 ,  H01L21/48 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H01L29/66 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01R12/523 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/09063 ,  H05K2201/10303 ,  H05K2201/1034 ,  H05K2201/10378 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/1059 ,  H05K2201/10606 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/041 ,  H05K3/325 ,  H05K3/3405 ,  H05K3/366 ,  H05K3/368

Abstract: 3D electrical integration is provided by connecting several component carriers to a single substrate using contacts at the edges of the component carriers making contact to a 2D contact array (e.g., a ball grid array or the like) on the substrate. The resulting integration of components on the component carriers is 3D, thereby providing much higher integration density than in 2D approaches.

公开(公告)号：WO2021229142A1

公开(公告)日：2021-11-18

申请号：PCT/FI2021/050329

申请日：2021-05-04

Applicant: TACTOTEK OY

Inventor： HÄNNINEN, Ilpo ,  SÄÄSKI, Jarmo ,  HEIKKINEN, Mikko

IPC: H05K3/28 ,  H05K1/02 ,  H05K1/18 ,  H01R12/722 ,  H01R12/724 ,  H01R13/504 ,  H01R43/205 ,  H01R43/24 ,  H05K1/0284 ,  H05K1/185 ,  H05K2201/0129 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/1034 ,  H05K2203/1316 ,  H05K2203/1327 ,  H05K3/284

Abstract: Integrated multilayer structure (100, 200, 240, 280, 400,580, 640, 740, 900, 1300, 1400) comprising: a substrate film (102) comprising electrically substantially insulating material; a circuit design (106, 108, 109) comprising electrically conductive elements (106) provided on the substrate film, said conductive elements defining a number of contact areas (107); a connector (110) at the edge (102E) of the substrate film, the connector comprising a number of electrically conductive elongated contact elements (118), such as pins, connected to the contact areas of the conductive elements of the circuit design on the substrate film while further extending from the substrate film to couple to an external connecting element (112) responsive to mating the external connecting element with the connector; and at least one plastic layer (104, 104B, 105) molded onto the substrate film so as to at least partially cover the circuit design and only partially cover the connector, the covered portions including connection points of the contact elements with the contact areas and at least partially excluding the extended portions of the contact elements configured to couple to the external connecting element. A corresponding method of manufacture is presented.