公开(公告)号：US08158508B2

公开(公告)日：2012-04-17

申请号：US11981125

申请日：2007-10-31

Applicant: Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

Inventor： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC: H01L21/44

CPC classification number: H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/06136 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract translation: 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US07902679B2

公开(公告)日：2011-03-08

申请号：US11981138

申请日：2007-10-31

Applicant: Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

Inventor： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/06136 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract translation: 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US20110024905A1

公开(公告)日：2011-02-03

申请号：US12852467

申请日：2010-08-07

Applicant: Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

Inventor： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/06136 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract translation: 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US07465653B2

公开(公告)日：2008-12-16

申请号：US10962964

申请日：2004-10-12

Applicant: Ching-Cheng Huang ,  Chuen-Jye Lin ,  Ming-Ta Lei ,  Mou-Shiung Lin

Inventor： Ching-Cheng Huang ,  Chuen-Jye Lin ,  Ming-Ta Lei ,  Mou-Shiung Lin

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/02166 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05093 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Abstract translation: 根据本发明的目的，提供了一种在I / O焊盘的表面上形成金属凸块的新方法。 接触垫设置在电介质层的表面上。 在晶片级半导体器件测试期间用作I / O焊盘的I / O焊盘的铝在使用金属干燥的方法的表面积小于接触焊盘的表面积的情况下被完全或部分地去除 蚀刻或湿蚀刻。 接触焊盘可以通过在接触焊盘的平面中产生的互连金属或通过已经沉积接触焊盘的电介质层提供的通孔来访问。 通过在用于保护接触焊盘的钝化层上的聚酰亚胺层的沉积，图案化和蚀刻可以进一步扩展该工艺。

公开(公告)号：US20080113504A1

公开(公告)日：2008-05-15

申请号：US11930224

申请日：2007-10-31

Applicant: Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L21/441

CPC classification number: H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US20080111236A1

公开(公告)日：2008-05-15

申请号：US11930213

申请日：2007-10-31

Applicant: Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L23/488

CPC classification number: H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Abstract translation: 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US07355288B2

公开(公告)日：2008-04-08

申请号：US11120234

申请日：2005-05-02

Applicant: Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Abstract translation: 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US20080067677A1

公开(公告)日：2008-03-20

申请号：US11981138

申请日：2007-10-31

Applicant: Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

Inventor： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/06136 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract translation: 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。

公开(公告)号：US07105920B2

公开(公告)日：2006-09-12

申请号：US10988100

申请日：2004-11-12

Applicant: Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

Inventor： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

IPC: H01L23/12

CPC classification number: H05K1/0271 ,  H01L23/13 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

Abstract translation: 提供了提高芯片封装可靠性的基板设计。 芯片封装包括在凹部中形成有陶瓷层的基板。 模具附着在陶瓷层上的衬底上。 基板可以附接到印刷电路板。 衬底可以通过在诸如由有机电介质材料形成的多层衬底的衬底中形成凹陷来制造。 然后将陶瓷层固定在凹槽中的基底上。 可以将模具连接到陶瓷层，并且基板可以附接到印刷电路板。

公开(公告)号：US20060163729A1

公开(公告)日：2006-07-27

申请号：US11389717

申请日：2006-03-27

Applicant: Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

Inventor： Mou-Shiung Lin ,  Ming-Ta Lei ,  Chuen-Jye Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05099

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract translation: 提供了一种新的方法和封装，用于安装已经提供有小间距输入/输出互连凸块的半导体器件。 由柱状金属和焊料凸点组成的细间距焊料凸块直接施加到半导体器件的I / O焊盘，然后将器件倒装芯片接合到基板上。 可以为设备的I / O焊盘布置以便需要对器件的附加机械支撑的情况下提供虚拟凸块。