公开(公告)号：US20220216180A1

公开(公告)日：2022-07-07

申请号：US17579259

申请日：2022-01-19

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L21/68

Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

公开(公告)号：US11335647B2

公开(公告)日：2022-05-17

申请号：US16833445

申请日：2020-03-27

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01L21/56 ,  H01L23/552 ,  H01L23/31

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

公开(公告)号：US20220005827A1

公开(公告)日：2022-01-06

申请号：US17362557

申请日：2021-06-29

Applicant: Invensas Corporation

Inventor： Xu Chang ,  Belgacem Haba ,  Rajesh Katkar ,  David Edward Fisch ,  Javier A. Delacruz

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Techniques for manufacturing memory devices, such as 3-dimensional NAND (3D-NAND) memory devices, may include splitting gate planes (e.g., the planes that include the word lines) into strips, thereby splitting the memory cells and increasing a density of memory cells for a respective memory device. The techniques described herein are applicable to various types of 3D-NAND or other memory devices.

公开(公告)号：US20210225811A1

公开(公告)日：2021-07-22

申请号：US17217749

申请日：2021-03-30

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Javier A. Delacruz

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

公开(公告)号：US20200321275A1

公开(公告)日：2020-10-08

申请号：US16837948

申请日：2020-04-01

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Stephen Morein ,  Ilyas Mohammed ,  Rajesh Katkar ,  Javier A. Delacruz

IPC: H01L23/50 ,  H01L23/367 ,  H01L23/49 ,  H01L23/64 ,  H01L21/48

Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

公开(公告)号：US10299368B2

公开(公告)日：2019-05-21

申请号：US15387278

申请日：2016-12-21

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01P1/207 ,  H05K1/02 ,  H05K3/30 ,  H01P1/208 ,  H01P3/12 ,  H01P1/39 ,  H01P5/19 ,  H01P7/06 ,  H01P11/00 ,  H01Q13/18

Abstract: Apparatus, and corresponding method, relates generally to a microelectronic device. In such an apparatus, a first conductive layer is for providing a lower interior surface of a circuit structure. A plurality of wire bond wires are interconnected to the lower interior surface and spaced apart from one another for providing at least one side of the circuit structure. A second conductive layer is for providing an upper interior surface of the circuit structure spaced apart from the lower interior surface by and interconnected to the plurality of wire bond wires. The plurality of wire bond wires, the first conductive layer and the second conductive layer in combination define at least one opening in the at least one side for a signal port of the circuit structure. Such circuit structure may be a signal guide circuit structure, such as for a signal waveguide or signal cavity for example.

公开(公告)号：US10283445B2

公开(公告)日：2019-05-07

申请号：US15334606

申请日：2016-10-26

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Wael Zohni ,  Liang Wang ,  Akash Agrawal

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

公开(公告)号：US20190069392A1

公开(公告)日：2019-02-28

申请号：US16172271

申请日：2018-10-26

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz ,  Belgacem Haba

IPC: H05K1/02 ,  H05K3/10 ,  H01L21/48 ,  H05K1/11 ,  H03H7/38 ,  H05K1/18 ,  H01L23/498 ,  H01L23/66 ,  H01P5/02 ,  H01P3/08 ,  H01P3/02 ,  H01P3/18 ,  H01P11/00

Abstract: A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.

公开(公告)号：US20180261556A1

公开(公告)日：2018-09-13

申请号：US15977905

申请日：2018-05-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Sangil Lee ,  Craig Mitchell ,  Gabriel Z. Guevara ,  Javier A. Delacruz

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  B23K1/00

CPC classification number: H01L23/562 ,  B23K1/0008 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012

Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

公开(公告)号：US20180033764A1

公开(公告)日：2018-02-01

申请号：US15237936

申请日：2016-08-16

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Javier A. Delacruz

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L24/49 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.