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    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF
    2.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230317739A1

    公开(公告)日：2023-10-05

    申请号：US18130444

    申请日：2023-04-04

    Applicant: Sharp Display Technology Corporation

    Inventor： Hajime IMAI ,  Tohru DAITOH ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

    IPC: H01L27/12

    CPC classification number: H01L27/1248 ,  H01L27/1288

    Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer. Each of the hydrogen desorption amount of the lower layer and the hydrogen desorption amount of the intermediate layer is a desorption amount of hydrogen molecules per unit thickness in a range from 25° C. to 600° C. by TDS analysis.

    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220285405A1

    公开(公告)日：2022-09-08

    申请号：US17686485

    申请日：2022-03-04

    Applicant: Sharp Display Technology Corporation

    Inventor： Hajime IMAI ,  Tohru DAITOH ,  Teruyuki UEDA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

    IPC: H01L27/12 ,  G06F3/041

    Abstract: An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, in which each of oxide semiconductor TFT includes an oxide semiconductor layer including a first region and a second region having a specific resistance lower than a specific resistance of the first region, and a gate electrode disposed on at least a part of the first region with a gate insulating layer interposed therebetween, the gate insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and, when viewed from a normal direction of the substrate, the first insulating layer overlaps with the first region and does not overlap with the second region and the second insulating layer overlaps with the first region and at least a part of the second region.

    ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE
    4.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE 审中-公开

    公开(公告)号：US20240288738A1

    公开(公告)日：2024-08-29

    申请号：US18407420

    申请日：2024-01-08

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

    IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

    CPC classification number: G02F1/13629 ,  G02F1/1368 ,  H01L27/124

    Abstract: An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.

    ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE
    5.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE 有权

    公开(公告)号：US20230082232A1

    公开(公告)日：2023-03-16

    申请号：US17903085

    申请日：2022-09-06

    Applicant: Sharp Display Technology Corporation

    Inventor： Tatsuya KAWASAKI ,  Tohru DAITOH ,  Hajime IMAI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Yoshiharu HIRATA ,  Yoshihito HARA

    IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

    Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

    DISPLAY DEVICE
    6.
    发明申请
    DISPLAY DEVICE 有权

    公开(公告)号：US20250149007A1

    公开(公告)日：2025-05-08

    申请号：US18913037

    申请日：2024-10-11

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Yoshihito HARA ,  Jun NISHIMURA ,  Yohei TAKEUCHI

    IPC: G09G3/36 ,  G06F3/041

    Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.

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