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    SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240154038A1

    公开(公告)日：2024-05-09

    申请号：US18378165

    申请日：2023-10-10

    Applicant: Sharp Display Technology Corporation

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

    IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/417 ,  H01L29/66 ,  H10K59/121

    CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L29/41733 ,  H01L29/6675 ,  H01L29/78696 ,  H10K59/1213

    Abstract: A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode. The first gate insulating layer includes a first layer and a second layer provided on the first layer. The second layer of the first gate insulating layer and the second gate insulating layer are provided in the same layer.

    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE
    4.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20230418123A1

    公开(公告)日：2023-12-28

    申请号：US18211805

    申请日：2023-06-20

    Applicant: Sharp Display Technology Corporation

    Inventor： Hitoshi TAKAHATA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA

    IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

    CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/1225

    Abstract: An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.

    ACTIVE MATRIX SUBSTRATE
    5.
    发明申请
    ACTIVE MATRIX SUBSTRATE 有权

    公开(公告)号：US20230135065A1

    公开(公告)日：2023-05-04

    申请号：US17973790

    申请日：2022-10-26

    Applicant: Sharp Display Technology Corporation

    Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

    IPC: H01L27/12

    Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer. The plurality of oxide semiconductor TFTs include a first TFT including an oxide semiconductor layer extending across the first gate wiring line and the second gate wiring line in the column direction, when viewed from a normal direction of the substrate. Portions of the first gate wiring line and the second gate wiring line, over which the oxide semiconductor layer of the first TFT extends, respectively function as the lower gate electrode and the upper gate electrode of the first TFT. When viewed from the normal direction of the substrate, the first gate wiring line includes a plurality of first notched portions disposed spaced apart from each other and a first solid portion, the first solid portion being a portion other than the plurality of first notch portions. When viewed from the normal direction of the substrate, the second gate wiring line includes a second solid portion including a plurality of first overlapping portions disposed spaced apart from each other, each of the first overlapping portions partially overlapping at least one of the plurality of first notched portions, and a second overlapping portion overlapping the first solid portion. When viewed from the normal direction of the substrate, the second overlapping portion continuously extends from one of two of the plurality of source wiring lines adjacent to each other, to the other of the two source wiring lines adjacent to each other.

    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME
    6.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME 有权

    公开(公告)号：US20230075289A1

    公开(公告)日：2023-03-09

    申请号：US17895226

    申请日：2022-08-25

    Applicant: Sharp Display Technology Corporation

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

    IPC: H01L29/786 ,  H01L29/417 ,  H01L27/32 ,  H01L29/66

    Abstract: An active matrix substrate includes: a first oxide semiconductor layer including a first channel region; a first gate electrode disposed on the substrate side of the first oxide semiconductor layer; a channel protection layer disposed on a side of the first oxide semiconductor layer opposite to the substrate and covering the first channel region; a first TFT having a first source electrode and a first drain electrode in an upper layer of the channel protection layer; a second oxide semiconductor layer; a second gate electrode disposed on a side of the second oxide semiconductor layer opposite to the substrate; and the second TFT having a second source electrode and a second drain electrode disposed on an interlayer insulating layer that covers the second gate electrode, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed of the same layered oxide semiconductor film, the layered oxide semiconductor film has a layered structure including a high mobility oxide semiconductor film and a low mobility oxide semiconductor film disposed on the substrate side of the high mobility oxide semiconductor film and having a lower mobility than a mobility of the high mobility oxide semiconductor film, and the channel protection layer of the first TFT and the gate insulating layer of the second TFT are formed of the same insulating film.

    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF
    7.
    发明公开
    ACTIVE MATRIX SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230317739A1

    公开(公告)日：2023-10-05

    申请号：US18130444

    申请日：2023-04-04

    Applicant: Sharp Display Technology Corporation

    Inventor： Hajime IMAI ,  Tohru DAITOH ,  Yoshihito HARA ,  Tetsuo KIKUCHI ,  Teruyuki UEDA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA

    IPC: H01L27/12

    CPC classification number: H01L27/1248 ,  H01L27/1288

    Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer. Each of the hydrogen desorption amount of the lower layer and the hydrogen desorption amount of the intermediate layer is a desorption amount of hydrogen molecules per unit thickness in a range from 25° C. to 600° C. by TDS analysis.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220406942A1

    公开(公告)日：2022-12-22

    申请号：US17835273

    申请日：2022-06-08

    Applicant: Sharp Display Technology Corporation

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA

    IPC: H01L29/786

    Abstract: Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer. In the channel region, the thickness of the upper layer is equal to or less than 1/3 of the thickness of the lower layer, and the thickness of the high mobility layer is equal to or less than 1/2 of the thickness of the lower layer.

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