公开(公告)号：US09887145B2

公开(公告)日：2018-02-06

申请号：US14678278

申请日：2015-04-03

Applicant: Dawning Leading Technology Inc.

Inventor： Diann-Fang Lin

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/043 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/04 ,  H01L23/433 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/34 ,  H01L23/04 ,  H01L23/24 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/167 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A meal top stacking package structure and a method for manufacturing the same are provided, wherein the metal top stacking package structure includes a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure.

公开(公告)号：US09607933B2

公开(公告)日：2017-03-28

申请号：US14176022

申请日：2014-02-07

Applicant: DAWNING LEADING TECHNOLOGY INC

Inventor： Diann Fang Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/181 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A lead frame structure for quad flat no-lead (QFN) package includes a main base, a plurality of terminals and a first metal layer. The main base has a center area for carrying a semiconductor die, and a periphery area surrounding the center area. The plurality of terminals are arranged around the main base. The first metal layer has a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals. Wherein the main base and the plurality of terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process.

公开(公告)号：US09478512B2

公开(公告)日：2016-10-25

申请号：US14619404

申请日：2015-02-11

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Yu-Shan Hu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05609 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105

Abstract: A semiconductor packaging structure includes a chip, a metal barrier layer, a dielectric layer and two metal seed layers. The chip has a top surface, connection pads on the top surface, and a passivation layer on the top surface and partly covering the connection pads. The metal barrier layer is disposed on each of the connection pads; the dielectric layer is disposed on the passivation layer and the metal barrier layer, and has through holes to expose the metal barrier layer. The first of the metal seed layers is disposed on the dielectric layer and the exposed metal barrier layer, while the second metal seed layer is disposed on the first metal seed layer. Therefore, the metal barrier layer can effectively prevent damage to the connection pads of the chip during the manufacturing process.

Abstract translation: 半导体封装结构包括芯片，金属阻挡层，电介质层和两个金属种子层。 该芯片具有顶表面，顶表面上的连接焊盘和顶表面上的钝化层，并部分覆盖连接焊盘。 金属阻挡层设置在每个连接焊盘上; 电介质层设置在钝化层和金属阻挡层上，并且具有通孔以暴露金属阻挡层。 第一金属种子层设置在电介质层和暴露的金属阻挡层上，而第二金属种子层设置在第一金属籽晶层上。 因此，金属阻挡层可以有效地防止在制造过程中损坏芯片的连接焊盘。

公开(公告)号：US20130065363A1

公开(公告)日：2013-03-14

申请号：US13327491

申请日：2011-12-15

Applicant: Diann-Fang Lin

Inventor： Diann-Fang Lin

IPC: H01L21/58 ,  H01L21/60

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48265 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a chip packaging structure is disclosed. The manufacturing method includes steps of: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; placing a chip on the adhesion layer; and electrically connecting the chip to the conductive trace layer. Via these arrangements, the chip packaging structure made by the manufacturing method can have a smaller thickness.

Abstract translation: 公开了一种制造芯片封装结构的方法。 该制造方法包括以下步骤：提供保护层; 在保护层上形成导电迹线层; 在导电迹线层上形成粘附层; 将芯片放置在粘合层上; 并且将所述芯片电连接到所述导电迹线层。 通过这些布置，通过制造方法制造的芯片封装结构可以具有更小的厚度。

公开(公告)号：US20130062783A1

公开(公告)日：2013-03-14

申请号：US13606147

申请日：2012-09-07

Applicant: Diann-Fang LIN

Inventor： Diann-Fang LIN

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.

Abstract translation: 提供了一种芯片封装结构及其制造方法。 芯片封装结构包括第一芯片，第二芯片和转移部件。 第一芯片具有形成在第一芯片的顶表面上的多个第一焊盘。 第二芯片具有形成在第二芯片的顶表面上的多个第二焊盘。 第一芯片和第二芯片彼此并排布置并电连接。 转印组分设置在第一芯片的顶表面上并与第一芯片电连接。 通过这些布置，芯片封装结构可以具有更小的尺寸。

公开(公告)号：US09161446B2

公开(公告)日：2015-10-13

申请号：US14160452

申请日：2014-01-21

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Diann Fang Lin

IPC: H05K1/11 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K1/115 ,  H01H2207/04 ,  H01H2227/018 ,  H05K1/16 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/10053 ,  H05K2201/10265 ,  H05K2201/1031 ,  Y02P70/611

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract translation: 微电子部件结构包括绝缘体，至少一个导电通孔，至少一个导电材料和至少一个微型端子。 绝缘体具有顶表面和底表面。 导电通孔穿透顶面和底面。 导电材料形成在导电通孔中。 微型端子设置在导电材料之上。

公开(公告)号：US08962390B2

公开(公告)日：2015-02-24

申请号：US13327491

申请日：2011-12-15

Applicant: Diann-Fang Lin

Inventor： Diann-Fang Lin

IPC: H01L21/00 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48265 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a chip packaging structure is disclosed. The manufacturing method includes steps of: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; placing a chip on the adhesion layer; and electrically connecting the chip to the conductive trace layer. Via these arrangements, the chip packaging structure made by the manufacturing method can have a smaller thickness.

Abstract translation: 公开了一种制造芯片封装结构的方法。 该制造方法包括以下步骤：提供保护层; 在保护层上形成导电迹线层; 在导电迹线层上形成粘附层; 将芯片放置在粘合层上; 并且将所述芯片电连接到所述导电迹线层。 通过这些布置，通过制造方法制造的芯片封装结构可以具有更小的厚度。

公开(公告)号：US20140202754A1

公开(公告)日：2014-07-24

申请号：US14160452

申请日：2014-01-21

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： DIANN FANG LIN

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01H2207/04 ,  H01H2227/018 ,  H05K1/16 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/10053 ,  H05K2201/10265 ,  H05K2201/1031 ,  Y02P70/611

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract translation: 微电子部件结构包括绝缘体，至少一个导电通孔，至少一个导电材料和至少一个微型端子。 绝缘体具有顶表面和底表面。 导电通孔穿透顶面和底面。 导电材料形成在导电通孔中。 微型端子设置在导电材料之上。

公开(公告)号：US10651146B2

公开(公告)日：2020-05-12

申请号：US13606147

申请日：2012-09-07

Applicant: Diann-Fang Lin

Inventor： Diann-Fang Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.

公开(公告)号：US09892988B2

公开(公告)日：2018-02-13

申请号：US14277256

申请日：2014-05-14

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Yu-Shan Hu ,  Diann-Fang Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05099 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased.