公开(公告)号：US20160240512A1

公开(公告)日：2016-08-18

申请号：US14620705

申请日：2015-02-12

Applicant: Dawning Leading Technology Inc.

Inventor： Diann-Fang LIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package structure comprises a substrate including a plurality of electrical connecting pad; a first chip with a lower surface stacked on the substrate; a second chip stacked on an upper surface of the first chip by a interlaced reciprocation stacking way; a spacer stacked on an upper surface of the second chip by the interlaced reciprocation stacking way; and third chip stacked on the an upper surface of the spacer by the interlaced reciprocation stacking way, so that a first spacing is formed between an end of the third and an end of the spacer. Thereby, a position of a stress point is changed to reduce a risk of the chip crack during wire bonding.

Abstract translation: 本发明涉及一种多芯片堆叠封装结构及其制造方法，其中多芯片堆叠封装结构包括：一个包括多个电连接焊盘的衬底; 第一芯片，其具有堆叠在所述基板上的下表面; 第二芯片，通过隔行扫描堆叠方式堆叠在第一芯片的上表面上; 通过隔行扫描堆叠方式堆叠在第二芯片的上表面上的间隔件; 以及通过隔行扫描堆叠方式堆叠在间隔物的上表面上的第三芯片，使得在间隔件的第三端和端部的端部之间形成第一间隔。 因此，应力点的位置被改变以减少引线接合期间芯片裂纹的风险。

公开(公告)号：US09887145B2

公开(公告)日：2018-02-06

申请号：US14678278

申请日：2015-04-03

Applicant: Dawning Leading Technology Inc.

Inventor： Diann-Fang Lin

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/043 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/04 ,  H01L23/433 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/34 ,  H01L23/04 ,  H01L23/24 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/167 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A meal top stacking package structure and a method for manufacturing the same are provided, wherein the metal top stacking package structure includes a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure.

公开(公告)号：US09607933B2

公开(公告)日：2017-03-28

申请号：US14176022

申请日：2014-02-07

Applicant: DAWNING LEADING TECHNOLOGY INC

Inventor： Diann Fang Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/181 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A lead frame structure for quad flat no-lead (QFN) package includes a main base, a plurality of terminals and a first metal layer. The main base has a center area for carrying a semiconductor die, and a periphery area surrounding the center area. The plurality of terminals are arranged around the main base. The first metal layer has a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals. Wherein the main base and the plurality of terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process.

公开(公告)号：US09478512B2

公开(公告)日：2016-10-25

申请号：US14619404

申请日：2015-02-11

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Yu-Shan Hu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05609 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105

Abstract: A semiconductor packaging structure includes a chip, a metal barrier layer, a dielectric layer and two metal seed layers. The chip has a top surface, connection pads on the top surface, and a passivation layer on the top surface and partly covering the connection pads. The metal barrier layer is disposed on each of the connection pads; the dielectric layer is disposed on the passivation layer and the metal barrier layer, and has through holes to expose the metal barrier layer. The first of the metal seed layers is disposed on the dielectric layer and the exposed metal barrier layer, while the second metal seed layer is disposed on the first metal seed layer. Therefore, the metal barrier layer can effectively prevent damage to the connection pads of the chip during the manufacturing process.

Abstract translation: 半导体封装结构包括芯片，金属阻挡层，电介质层和两个金属种子层。 该芯片具有顶表面，顶表面上的连接焊盘和顶表面上的钝化层，并部分覆盖连接焊盘。 金属阻挡层设置在每个连接焊盘上; 电介质层设置在钝化层和金属阻挡层上，并且具有通孔以暴露金属阻挡层。 第一金属种子层设置在电介质层和暴露的金属阻挡层上，而第二金属种子层设置在第一金属籽晶层上。 因此，金属阻挡层可以有效地防止在制造过程中损坏芯片的连接焊盘。

公开(公告)号：US20150357288A1

公开(公告)日：2015-12-10

申请号：US14457356

申请日：2014-08-12

Applicant: Dawning Leading Technology Inc.

Inventor： Diann-Fang LIN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/64 ,  H01L23/645 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A packaging structure for thin die is provided. The packaging structure has a substrate, a thin die, a strengthening layer and an encapsulation body. The thin die is disposed on and electrically connected with the substrate; the strengthening layer is disposed on the thin die; and the encapsulation body is formed on the substrate and covers both the thin die and the strengthening layer. The strengthening layer can bear pressure or stress during the formation of the encapsulation body to protect the thin die. A method for manufacturing the packaging structure for the thin die is further provided to manufacture the above packaging structure for the thin die.

Abstract translation: 提供了用于薄模的封装结构。 封装结构具有基板，薄模，强化层和封装体。 薄模设置在基板上并与基板电连接; 强化层设置在薄模上; 并且所述封装体形成在所述基板上并覆盖所述薄模和所述强化层。 加强层在形成封装体期间可承受压力或应力，以保护薄模。 还提供了用于制造薄模的包装结构的方法以制造用于薄模的上述包装结构。

公开(公告)号：US20160293509A1

公开(公告)日：2016-10-06

申请号：US14678278

申请日：2015-04-03

Applicant: Dawning Leading Technology Inc.

Inventor： Diann-Fang LIN

IPC: H01L23/06 ,  H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/34 ,  H01L23/04 ,  H01L23/24 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/167 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention relates to a meal top stacking package structure and a method for manufacturing the same, wherein the metal top stacking package structure comprises a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure.

Abstract translation: 本发明涉及一种餐后堆积包装结构及其制造方法，其中金属顶层叠包装结构包括一个包括上表面和下表面的金属基底和形成在上表面的模具接受腔; 第一芯片，通过第一粘合层固定在模具接收器腔上; 具有上表面的基板; 通过第二粘合层固定在所述基板的上表面上的第二芯片; 以及形成在所述基板的上表面上的多个连接部件; 其中金属基底的上表面通过连接部件与基底连接。 因此，结构和方法可以增强堆叠包装结构的散热和电磁屏蔽。

公开(公告)号：US09161446B2

公开(公告)日：2015-10-13

申请号：US14160452

申请日：2014-01-21

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Diann Fang Lin

IPC: H05K1/11 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K1/115 ,  H01H2207/04 ,  H01H2227/018 ,  H05K1/16 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/10053 ,  H05K2201/10265 ,  H05K2201/1031 ,  Y02P70/611

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract translation: 微电子部件结构包括绝缘体，至少一个导电通孔，至少一个导电材料和至少一个微型端子。 绝缘体具有顶表面和底表面。 导电通孔穿透顶面和底面。 导电材料形成在导电通孔中。 微型端子设置在导电材料之上。

公开(公告)号：US20140202754A1

公开(公告)日：2014-07-24

申请号：US14160452

申请日：2014-01-21

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： DIANN FANG LIN

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01H2207/04 ,  H01H2227/018 ,  H05K1/16 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/10053 ,  H05K2201/10265 ,  H05K2201/1031 ,  Y02P70/611

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract translation: 微电子部件结构包括绝缘体，至少一个导电通孔，至少一个导电材料和至少一个微型端子。 绝缘体具有顶表面和底表面。 导电通孔穿透顶面和底面。 导电材料形成在导电通孔中。 微型端子设置在导电材料之上。

公开(公告)号：US09892988B2

公开(公告)日：2018-02-13

申请号：US14277256

申请日：2014-05-14

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Yu-Shan Hu ,  Diann-Fang Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05099 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased.

公开(公告)号：US09646937B2

公开(公告)日：2017-05-09

申请号：US14457356

申请日：2014-08-12

Applicant: DAWNING LEADING TECHNOLOGY INC.

Inventor： Diann-Fang Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/64 ,  H01L23/645 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A packaging structure for thin die is provided. The packaging structure has a substrate, a thin die, a strengthening layer and an encapsulation body. The thin die is disposed on and electrically connected with the substrate; the strengthening layer is disposed on the thin die; and the encapsulation body is formed on the substrate and covers both the thin die and the strengthening layer. The strengthening layer can bear pressure or stress during the formation of the encapsulation body to protect the thin die. A method for manufacturing the packaging structure for the thin die is further provided to manufacture the above packaging structure for the thin die.