公开(公告)号：US12127329B2

公开(公告)日：2024-10-22

申请号：US17612010

申请日：2020-05-29

Applicant: HELLA GMBH & CO KGAA ,  INFINITE FLEX GMBH

Inventor： Dirk Bösch ,  Kangkai Ma

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H01L33/64 ,  H05K1/18 ,  H05K7/20

CPC classification number: H05K1/0204 ,  H05K1/118 ,  H05K3/0061 ,  H01L33/64 ,  H01L33/647 ,  H05K1/0207 ,  H05K1/189 ,  H05K7/205 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/066 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2203/0522

Abstract: A flexible circuit board includes an electrically insulating cover layer, at least one electrical component arranged on the upper side of the cover layer with electrical contacts, a conducting track structure arranged on the underside of the cover layer and with contact regions, wherein the electrical contacts are each electrically conductively connected to one of the contact regions through one of a plurality of openings in the cover layer, a heat sink which is thermally conductively connected to each electrical component through the cover layer, and a layer with high conductivity. To create an improved cooling capacity of the electrical component, the heat arising in the electrical components is first dissipated effectively within the conducting paths of the conducting path structure and then dissipated out of the conducting paths directly into the heat sink by the layer with high heat conductivity.

公开(公告)号：US11937366B2

公开(公告)日：2024-03-19

申请号：US17701964

申请日：2022-03-23

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Tzu Hsuan Wang ,  Yu Cheng Lin

IPC: H05K1/02

CPC classification number: H05K1/024 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/0195

Abstract: A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.

公开(公告)号：US20230352384A1

公开(公告)日：2023-11-02

申请号：US18188622

申请日：2023-03-23

Applicant: Lumentum Operations LLC

Inventor： Wei SHI ,  Mikhail DOLGANOV ,  Steve CHEUNG ,  Lijun ZHU

IPC: H01L23/498 ,  H05K3/46 ,  H05K1/11 ,  H05K1/03 ,  H05K1/16

CPC classification number: H01L23/49822 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/09563

Abstract: In some implementations, a substrate comprises a ceramic core, multiple metal-filled vias through the ceramic core, and a first metal layer, on a top side of the ceramic core, including metal traces, over respective metal-filled vias. The substrate comprises a second metal layer, including a first electrical contact over a first metal trace, a second electrical contact over a second metal trace, and a third electrical contact over a third metal trace, where the second metal trace is electrically isolated from the first and third metal traces. The substrate comprises a thin dielectric layer separating the first metal layer and the second metal layer. The dielectric layer between the first metal layer and the second layer provides the substrate with a low parasitic inductance and a low thermal resistance based on a thickness of the dielectric layer and/or a material used for the dielectric layer.

公开(公告)号：US20180249576A1

公开(公告)日：2018-08-30

申请号：US15547851

申请日：2016-01-28

Applicant: FUJIKURA LTD.

Inventor： Shingo Ogura

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0283 ,  H01B5/14 ,  H05K1/02 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/1283 ,  H05K3/24 ,  H05K3/28 ,  H05K3/285 ,  H05K3/287 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2201/0187 ,  H05K2201/09227

Abstract: A stretchable wiring board includes: a stretchable base; at least one stretchable wiring provided on the stretchable base; and a poorly stretchable member provided so as to overlap at least part of the stretchable wiring in a thickness direction looking at the stretchable base in planar view. The poorly stretchable member suppresses change in a resistance value of the stretchable wiring associated with stretching deformation of the stretchable base. As a result, stable operability can be secured without affecting an operating voltage of an electronic component.

公开(公告)号：US10064280B2

公开(公告)日：2018-08-28

申请号：US15328190

申请日：2015-07-24

Applicant: LG INNOTEK CO., LTD.

Inventor： Jae Hyun Ahn ,  Min Wook Yu

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/184 ,  H01L33/486 ,  H01L33/62 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/115 ,  H05K1/185 ,  H05K3/007 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2203/1563

Abstract: A printed circuit board includes an insulating layer and an element embedded in the insulating layer and exposed through a surface of the insulating layer.

公开(公告)号：US09999134B2

公开(公告)日：2018-06-12

申请号：US15081623

申请日：2016-03-25

Applicant: Multek Technologies Limited

Inventor： Mark Zhang ,  Kwan Pen ,  Pui Yin Yu

IPC: H05K1/03 ,  H05K3/04 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K3/048 ,  H05K1/036 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09109 ,  H05K2201/0989 ,  H05K2203/0228 ,  H05K2203/1383

Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.

公开(公告)号：US09980380B2

公开(公告)日：2018-05-22

申请号：US15331987

申请日：2016-10-24

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Rainer Pludra ,  Dietmar Drofenik ,  Johannes Stahr ,  Siegfried Götzinger ,  Ljubomir Mareljic

IPC: H05K1/00 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K3/46 ,  H05K1/11 ,  H05K3/22

CPC classification number: H05K1/142 ,  H05K1/115 ,  H05K1/185 ,  H05K1/189 ,  H05K3/225 ,  H05K3/368 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/09163 ,  H05K2201/09845 ,  H05K2203/1461 ,  Y10T29/49155

Abstract: In a method for producing a printed circuit board consisting of at least two printed circuit regions, wherein the printed circuit board regions each compromise at least one conductive layer and/or at least one device or once conductive component, wherein printed circuit board regions to be connected to another one, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a coupling or connection, and wherein, after a coupling or connection of printed circuit board regions, at least one additional layer or ply of the printed circuit board is applied over the printed circuit board regions, the additional layer is embodied as a conductive layer, which is contact-connected via plated-through holes to conductive layers or devices or components integrated in the printed circuit board regions.

公开(公告)号：US20180108971A1

公开(公告)日：2018-04-19

申请号：US15295308

申请日：2016-10-17

Applicant: International Business Machines Corporation

Inventor： Samuel R. CONNOR ,  Jose A. HEJASE ,  Joseph KUCZYNSKI ,  Joshua C. Myers ,  Junyan TANG

IPC: H01P5/08 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/02 ,  H01P3/16 ,  H01P11/00

CPC classification number: H01P5/087 ,  H01P3/121 ,  H01P3/16 ,  H01P5/103 ,  H01P11/006 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/113 ,  H05K2201/0187 ,  H05K2201/09618

Abstract: Embodiments herein describe a high-speed communication channel in a PCB that includes a dielectric waveguide coupled at respective ends to coaxial vias. The dielectric waveguide includes a core and a cladding where the material of the core has a higher dielectric constant than the material of the cladding. Thus, electromagnetic signals propagating in the core are internally reflected at the interface between the core and cladding such that the electromagnetic signals are primary contained in the core. The coaxial vias include a center conductor and an outer conductor (or shield) which extend through one or more layers of the PCB. One of the coaxial vias radiates electromagnetic signals into the dielectric waveguide at a first end of the core while the other coaxial via receives the radiated signals at a second end of the core.

公开(公告)号：US09913367B2

公开(公告)日：2018-03-06

申请号：US14585657

申请日：2014-12-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Nobuto Managaki ,  Tadahiro Sasaki ,  Atsuko Iida ,  Yutaka Onozuka ,  Hiroshi Yamada

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K1/0222 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0187 ,  H05K2201/0195

Abstract: A wiring board of an embodiment includes a through via, a first insulating film disposed around the through via, a second insulating film disposed around the first insulating film, a third insulating film disposed around the second insulating film and a resin disposed around the third insulating film. The resin includes fillers. The second insulating film has a relative permittivity lower than a relative permittivity of the first insulating film. The third insulating film has a relative permittivity higher than a relative permittivity of the second insulating film.

公开(公告)号：US09807884B2

公开(公告)日：2017-10-31

申请号：US14579651

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H05K3/40 ,  H01G4/248 ,  H01G4/012 ,  H01G4/005 ,  H01G4/232 ,  H01L23/538 ,  H01L23/50 ,  H01G4/30 ,  H01L23/00 ,  H01L25/065

CPC classification number: H05K1/185 ,  H01G4/005 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.