公开(公告)号：US20140253256A1

公开(公告)日：2014-09-11

申请号：US14164939

申请日：2014-01-27

Applicant: Integrated Device Technology, Inc.

Inventor： Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Amar Sarbbasesh Basu

IPC: H03L1/02 ,  H03L7/00 ,  H03B5/12

CPC classification number: H03L1/02 ,  H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2200/0038 ,  H03B2200/005 ,  H03B2200/0098 ,  H03J2200/10 ,  H03L1/00 ,  H03L1/026 ,  H03L7/00 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/099 ,  H03L7/24

Abstract: A periodic signal generator includes a resonant LC tank circuit that generates a periodic reference signal at a first frequency at a differential output thereof. A temperature-responsive frequency compensation module is electrically coupled to the differential output of the resonant LC tank circuit. This module includes a temperature dependent voltage control module that generates a temperature dependent control voltage and an array of switchable capacitive modules that is electrically coupled to a first node of the differential output of the resonant LC tank circuit and responsive to the temperature dependent control voltage and a plurality of switching coefficients. The array of switchable capacitive modules includes a fixed capacitor having a first terminal electrically coupled to the first node and a voltage-controlled variable capacitor having a first terminal electrically coupled to the first node.

Abstract translation: 周期信号发生器包括谐振LC谐振电路，其在其差分输出处以第一频率产生周期性参考信号。 温度响应频率补偿模块电耦合到谐振LC谐振电路的差分输出。 该模块包括温度依赖性电压控制模块，其产生与温度相关的控制电压，以及阵列的可切换电容模块，其电耦合到谐振LC谐振电路的差分输出的第一节点，并且响应于与温度相关的控制电压和 多个切换系数。 可切换电容性模块的阵列包括具有电耦合到第一节点的第一端子的固定电容器和具有电耦合到第一节点的第一端子的压控可变电容器。

公开(公告)号：US08754673B1

公开(公告)日：2014-06-17

申请号：US13936900

申请日：2013-07-08

Applicant: Integrated Device Technology, Inc.

Inventor： Wei Wang ,  Yumin Zhang

IPC: H03K5/22

CPC classification number: H03K5/2481

Abstract: An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.

Abstract translation: 集成电路装置包括参考电压发生器，其被配置为产生相对于在其输入处接收的数据信号（DATA）的幅度变化而相反变化的自适应参考电压（Vref）。 该参考电压发生器包括具有至少两个可变阻抗元件的图腾柱布置，该可变阻抗元件具有与输入电容耦合（通过相应的电容器）的控制端。 电流镜电耦合到至少两个可变阻抗元件的图腾柱布置。 还包括一个比较器。 比较器具有接收自适应参考电压的第一输入端子和接收数据信号的第二输入端子。

公开(公告)号：US20040110346A1

公开(公告)日：2004-06-10

申请号：US10315573

申请日：2002-12-09

Applicant: Integrated Device Technology, Inc.

Inventor： Wei Tao

IPC: H01L021/336 ,  H01L029/94 ,  H01L031/113 ,  H01L031/119 ,  H01L031/062 ,  H01L029/76 ,  H01L021/4763

CPC classification number: H01L21/76897 ,  H01L21/76829 ,  H01L29/4933

Abstract: A self-aligned contact, and a method for fabricating the same, are provided. A conductive element having an overlying hydrogen silsesquioxane (HSQ)-based dielectric cap is formed over a semiconductor substrate. Dielectric sidewall spacers are then formed adjacent to sidewalls of the conductive element and the HSQ-based dielectric cap. A HSQ-based dielectric layer is formed over the resulting structure, and an inter-layer dielectric layer, such as TEOS, is formed over the HSQ-based dielectric layer. The inter-layer dielectric layer is then etched through a mask having an opening located over a sidewall spacer, a portion of the HSQ-based dielectric cap and a portion of the substrate. The etch (which may be a C5F8 based etch) has a high selectivity (e.g., about 20:1) with respect to the HSQ-based dielectric layer, thereby enabling the etch to stop on the HSQ-based dielectric layer. Another etch removes the exposed HSQ-based dielectric layer to expose the substrate.

Abstract translation: 提供自对准接触件及其制造方法。 具有覆盖氢倍半硅氧烷（HSQ）的电介质盖的导电元件形成在半导体衬底上。 然后在导电元件和基于HSQ的电介质盖的侧壁附近形成介电侧壁间隔物。 在所得结构上形成基于HSQ的电介质层，并且在基于HSQ的电介质层上形成诸如TEOS的层间电介质层。 然后通过具有开口的掩模蚀刻层间电介质层，该开口位于侧壁间隔物，基于HSQ的电介质盖的一部分和衬底的一部分之上。 蚀刻（其可以是基于C5F8的蚀刻）相对于基于HSQ的电介质层具有高选择性（例如，约20:1），从而使得蚀刻能够在基于HSQ的电介质层上停止。 另外的蚀刻去除暴露的基于HSQ的电介质层以露出衬底。

公开(公告)号：US20030233515A1

公开(公告)日：2003-12-18

申请号：US10173516

申请日：2002-06-14

Applicant: Integrated Device Technology, Inc.

Inventor： David Honig

IPC: G06F012/00

CPC classification number: G06F17/30949 ,  G06F17/30982

Abstract: An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary content addressable memory (CAM) array on the integrated circuit chip is coupled to receive the hashed output value. The binary CAM array provides an index value in response to the hashed output value if the hashed output value matches an entry of the binary CAM array. In a particular embodiment, the hardware hashing circuit can be configured to process character strings having different lengths (greater than the width of the binary CAM array) in response to one or more configuration bits. The hardware hashing circuit can include, an input register, Data Encryption Standard (DES) circuitry and exclusive OR circuitry.

Abstract translation: 提供具有用于接收字符串的端口的集成电路芯片。 集成电路芯片上的硬件散列电路被配置为对字符串执行散列函数，从而产生散列输出值。 集成电路芯片上的二进制内容可寻址存储器（CAM）阵列被耦合以接收散列输出值。 如果散列输出值与二进制CAM阵列的条目匹配，则二进制CAM阵列将响应散列输出值提供索引值。 在特定实施例中，硬件散列电路可被配置为响应于一个或多个配置位来处理具有不同长度（大于二进制CAM阵列的宽度）的字符串。 硬件散列电路可以包括输入寄存器，数据加密标准（DES）电路和异或电路。

公开(公告)号：US20030020509A1

公开(公告)日：2003-01-30

申请号：US09954355

申请日：2001-09-12

Applicant: Integrated Device Technology, Inc.

Inventor： Kong Lam Song ,  Peng Cheong Choe

IPC: G01R031/26

CPC classification number: G01R1/07314 ,  H01L21/67126

Abstract: An integral system for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain connected to the assembly strip. The assembly strips are then passed to a test apparatus that transmits test signals to the ICs through the formed leads. The IC devices are then separated from the assembly strip using a singulation apparatus, and the separated ICs are stored in tubes for delivery. Visual inspection is also performed at various stages.

Abstract translation: 一种集成电路（IC）的集成系统，用于在引线形成之后和在与组件条分离之前安装在组装条上。 IC在每个组装条上以行和列布置，使得每个IC的侧面连接到从组装条延伸的引线，并且每个IC的端部由组装带保持。 将条带装载到系统中并传送到第一工位，在该第一工位处切割和形成引线，同时每个IC的端部保持连接到组装条上。 组装条然后传递到通过形成的引线将测试信号传输到IC的测试装置。 然后使用分离装置将IC器件与组装条分开，并将分离的IC存储在用于输送的管中。 目视检查也在不同阶段进行。

公开(公告)号：US11372441B2

公开(公告)日：2022-06-28

申请号：US16521217

申请日：2019-07-24

Applicant: Integrated Device Technology, Inc.

Inventor： Michael John Rupert ,  Ernst J G den Broeder ,  Leonid Goldin

IPC: G06F1/10 ,  G06F1/03 ,  H03L7/07 ,  G06F1/12

Abstract: A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.

公开(公告)号：US11271566B2

公开(公告)日：2022-03-08

申请号：US16220399

申请日：2018-12-14

Applicant: Integrated Device Technology, Inc.

Inventor： Victor Korol ,  Roberto Aparicio Joo

IPC: H01L21/8252 ,  H03K19/094 ,  H01L23/31 ,  H01L23/532 ,  H02P9/30

Abstract: An apparatus includes a device comprising a semiconductor junction configured to generate a reference voltage, a voltage divider circuit, a comparator circuit, and a first output circuit. The voltage divider circuit may be configured to generate a first predetermined threshold voltage in response to the reference voltage. The comparator circuit may be configured to generate a first intermediate signal in response to a comparison of the first predetermined threshold voltage and an input signal. The first output circuit may be configured to generate a first output signal in response to the first intermediate signal.

公开(公告)号：US11211829B2

公开(公告)日：2021-12-28

申请号：US16371887

申请日：2019-04-01

Applicant: Integrated Device Technology, Inc.

Inventor： Jiangjian Huang ,  Feng Zhou ,  Zhitong Guo ,  Rui Liu

IPC: H01F27/42 ,  H01F37/00 ,  H01F38/00 ,  H02J50/27 ,  H02J50/10 ,  H02J50/23

Abstract: Embodiments described herein a method for controlling operating frequency for a wireless power charging system. Specifically, a transmitter coil at a wireless power transmitter is driven under an operating frequency and an input voltage. Deadtime information at the wireless power receiver is received, from a wireless power receiver having a receiver coil that receives wireless power from the transmitter coil. A microcontroller then determines, based on the received deadtime information or the operating frequency, whether the operating frequency deviates from a target operating frequency range. Based on the determination, one or both of the operating frequency or the input voltage are adjusted thereby causing the operating frequency to fall within the target operating frequency range.

公开(公告)号：US11171501B2

公开(公告)日：2021-11-09

申请号：US16368788

申请日：2019-03-28

Applicant: Integrated Device Technology, Inc.

Inventor： Siqiang Fan ,  Sercan Ipek ,  Eric Huang ,  Turev Acar

IPC: H02J7/00 ,  H02M3/07 ,  H02J7/02

Abstract: Embodiments described herein provides a battery charging circuit that boosts an input current and feeds the boosted input current to a battery for fast charging. Specifically, the battery charging circuit includes a low dropout regulator (LDO) for providing a voltage, a switch mode charger, coupled between the LDO and a battery, and a capacitor divider, coupled between the LDO and the battery, in parallel to the switch mode charger, for dividing the voltage outputted from the LDO by a factor.

公开(公告)号：US11171418B2

公开(公告)日：2021-11-09

申请号：US16267627

申请日：2019-02-05

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Tumay Kanar

IPC: H01Q3/00 ,  H01Q3/28 ,  H01Q21/24 ,  H01Q3/26 ,  H04B7/06 ,  H04B7/10 ,  H01Q21/06

Abstract: An apparatus includes a phased array antenna panel and one or more dual-polarization beam former circuits mounted on the phased array antenna panel. The phased array antenna panel generally comprises a plurality of dual-polarization antenna elements. The plurality of dual-polarization antenna elements are generally arranged in one or more groups. Each dual-polarization beam former circuit may be coupled to a respective group of the dual-polarization antenna elements. Each dual-polarization beam former circuit generally comprises a plurality of transceiver channels. Each transceiver channel generally comprises a horizontal channel and a vertical channel. Each dual-polarization beam former circuit provides polarization rotation through bias current control in each of the vertical and horizontal channels.