公开(公告)号：US20060151861A1

公开(公告)日：2006-07-13

申请号：US11035918

申请日：2005-01-13

Applicant: Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

Inventor： Jonathan Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC: H01L23/495

CPC classification number: H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Abstract translation: 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US07061077B2

公开(公告)日：2006-06-13

申请号：US10233248

申请日：2002-08-30

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/495

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

公开(公告)号：US20060006550A1

公开(公告)日：2006-01-12

申请号：US11180367

申请日：2005-07-12

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

公开(公告)号：US20050280126A1

公开(公告)日：2005-12-22

申请号：US11213182

申请日：2005-08-25

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

IPC: H01L23/48 ,  H01L21/76 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

公开(公告)号：US20050218300A1

公开(公告)日：2005-10-06

申请号：US10817195

申请日：2004-04-02

Applicant: Maria Clemens Quinones ,  Rajeev Joshi

Inventor： Maria Clemens Quinones ,  Rajeev Joshi

IPC: A61B5/00 ,  G02B6/42 ,  H01J40/14 ,  H01L31/00

CPC classification number: G02B6/4201 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An optocoupler package is disclosed. The optocoupler package includes a substrate comprising a leadframe and a molding compound, and a plurality of optocouplers, each optocoupler including (i) an optical emitter, (ii) an optical receiver, (iii) and an optically transmissive medium disposed between the optical emitter and optical receiver, where the optical emitter and the optical receiver are electrically coupled to the leadframe.

Abstract translation: 公开了一种光耦合器封装。 光耦合器包括包括引线框架和模制化合物的基板和多个光耦合器，每个光耦合器包括（i）光发射器，（ii）光接收器，（iii）和设置在光发射器 和光接收器，其中光发射器和光接收器电耦合到引线框架。

公开(公告)号：US06696321B2

公开(公告)日：2004-02-24

申请号：US10309661

申请日：2002-12-03

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2144

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US06627991B1

公开(公告)日：2003-09-30

申请号：US09546053

申请日：2000-04-10

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2334

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US06469384B2

公开(公告)日：2002-10-22

申请号：US09776341

申请日：2001-02-01

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L2348

CPC classification number: H01L23/145 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.