公开(公告)号：US09766673B2

公开(公告)日：2017-09-19

申请号：US14633438

申请日：2015-02-27

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  Krishnakanth V. Sistla ,  James G. Hermerding, II

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F1/20 ,  G06F15/00

CPC classification number: G06F1/263 ,  G06F1/206 ,  G06F1/3212 ,  G06F1/324 ,  G06F15/00 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/174

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

公开(公告)号：US09377841B2

公开(公告)日：2016-06-28

申请号：US13889785

申请日：2013-05-08

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Ian Steiner ,  Avinash Ananthakrishnan ,  Krishnakanth Sistla ,  Chris Poirier ,  Matthew Bace ,  Eric Dehaemer

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元以控制处理器的功率消耗，其中功率控制单元包括控制逻辑以减少最大操作 如果在第一时间段内发生第一数量的强制执行状态转换或在第二时间段内发生第二数量的强制执行状态转换，则处理器的频率。 描述和要求保护其他实施例。

公开(公告)号：US09336175B2

公开(公告)日：2016-05-10

申请号：US14732693

申请日：2015-06-06

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Buck W. Gremel ,  Robert G. Blankenship ,  Krishnakanth V. Sistla ,  Michael F. Cole

IPC: G06F13/40 ,  G06F1/32 ,  G06F13/42 ,  G06F15/16

CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F1/3253 ,  G06F13/4018 ,  G06F13/4221 ,  G06F15/16 ,  Y02D10/151

Abstract: Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。 在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。 更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。 还公开并要求保护其他实施例。