公开(公告)号：US12100623B2

公开(公告)日：2024-09-24

申请号：US17848191

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

公开(公告)号：US12051723B2

公开(公告)日：2024-07-30

申请号：US16719415

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Kerryann Marrietta Foley ,  Sayed Hasan ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.

公开(公告)号：US11996411B2

公开(公告)日：2024-05-28

申请号：US16913796

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Anh Phan ,  Nicole K. Thomas ,  Urusa Alaan ,  Seung Hoon Sung ,  Christopher M. Neumann ,  Willy Rachmady ,  Patrick Morrow ,  Hui Jae Yoo ,  Richard E. Schenker ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ehren Mannebach

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H10B12/00

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H10B12/056

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US11996362B2

公开(公告)日：2024-05-28

申请号：US17493715

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/30604 ,  H01L21/768 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/785 ,  H01L29/7851

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11948874B2

公开(公告)日：2024-04-02

申请号：US16914132

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/088 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L27/088 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

公开(公告)号：US20240105589A1

公开(公告)日：2024-03-28

申请号：US17936014

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Shao Ming Koh ,  Patrick Morrow ,  June Choi ,  Sukru Yemenicioglu ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

公开(公告)号：US11830933B2

公开(公告)日：2023-11-28

申请号：US16240369

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US20230197815A1

公开(公告)日：2023-06-22

申请号：US17556750

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L27/088

Abstract: Techniques to form wrap-around contacts in a stacked transistor architecture. An example includes a first source or drain region and a second source or drain region spaced from and over the first source or drain region. A conductive contact is on a top surface of the second source or drain and extends down one or more side surfaces of the second source or drain region such that the conductive contact is laterally adjacent to a bottom surface of the second source or drain region. In some cases, the conductive contact is also on a top surface of the first source or drain region, and/or extends down a side surface of the first source or drain region. In some cases, a second conductive contact is on a bottom surface of the first source or drain region, and may extend up a side surface the first source or drain region.

公开(公告)号：US20230189495A1

公开(公告)日：2023-06-15

申请号：US17546770

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Seenivasan Subramaniam

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: Techniques are provided herein to form semiconductor devices having conductive backside structures to couple various transistor structures. In some embodiments, a given conductive backside structure acts as a shunt interconnect between two transistors, such as between the gate of one transistor and the source or drain region of another transistor. In an example, an integrated circuit includes two transistor devices having semiconductor material extending between separate source and drain regions and different gate structures over or around the semiconductor material of the two transistor devices. A conductive backside structure may be formed from the backside of the integrated circuit (e.g., after removing all or most of the substrate), where the backside structure contacts the source or drain region of one transistor and the gate structure of the other transistor.

公开(公告)号：US11658183B2

公开(公告)日：2023-05-23

申请号：US17372345

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow ,  Stephen M. Cea

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0688 ,  H01L29/785

Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.