公开(公告)号：US09379074B2

公开(公告)日：2016-06-28

申请号：US14250317

申请日：2014-04-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1718 ,  H01L2224/32145 ,  H01L2224/45147 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die.

Abstract translation: 公开了一种通常涉及管芯堆叠的装置。 在这种装置中，包括基板。 第一接合通孔阵列包括从基板的第一表面延伸的第一长度的第一布线。 凸起互连阵列设置在第一表面上。 模具通过凸块互连阵列与衬底互连。 第二接合通孔阵列包括第二导线，每个第二导线的第二长度不同于从模具的第二表面延伸的第一长度。

公开(公告)号：US20160079169A1

公开(公告)日：2016-03-17

申请号：US14489358

申请日：2014-09-17

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

Abstract translation: 适于将集成电路组件彼此连接的互连（124）包括导电和/或涂覆有导电材料（144）的聚合物构件（130）。 在一些实施例中，这种互连替代金属接合线。 还提供其他功能。

公开(公告)号：US09226396B2

公开(公告)日：2015-12-29

申请号：US13797355

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/16 ,  H05K1/11 ,  H05K7/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Abstract translation: 中间体及其制备方法在本文中公开。 在一个实施例中，插入件包括具有第一和第二相对面的表面和多个孔的区域，每个孔从第一表面朝向第二表面沿第一方向延伸，其中氧化铝沿每个孔的壁延伸; 多个导电连接元件，其沿第一方向延伸，主要由铝构成，并通过至少氧化铝彼此电隔离; 第一导电路径，设置在第一表面处，用于与插入件外部的第一部件连接; 以及设置在所述第二表面处用于与所述插入件外部的第二部件连接的第二导电路径，其中所述第一和第二导电路径通过至少一些所述连接元件电连接。

公开(公告)号：US20150318344A1

公开(公告)日：2015-11-05

申请号：US14268899

申请日：2014-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Abstract translation: 制造集成电路封装的方法包括提供具有限定空腔的第一区域的处理晶片。 在第一区域形成电容器。 电容器具有一对电极，每对电极耦合到一对导电焊盘中的一个，其至少一个设置在处理晶片的下表面上。 还提供了具有上表面的插入件，其具有导电焊盘和设置在其上的至少一个半导体管芯。 芯片具有与内插器的再分配层（RDL）电导耦合的集成电路。 把手晶片的下表面被结合到插入件的上表面，使得模具设置在空腔的下方或内部，并且处理晶片的导电焊盘以金属间隔结合到插入件的导电焊盘上， 金属键。

公开(公告)号：US20150303157A1

公开(公告)日：2015-10-22

申请号：US14754293

申请日：2015-06-29

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/3213

CPC classification number: H01L24/11 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/0362 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05578 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05664 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/81815 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process.

公开(公告)号：US09117827B1

公开(公告)日：2015-08-25

申请号：US14268899

申请日：2014-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/00 ,  H01L21/56

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US20150206815A1

公开(公告)日：2015-07-23

申请号：US14157790

申请日：2014-01-17

Applicant: Invensas Corporation

Inventor： Rajesh Katkar

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/10 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83005 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.

Abstract translation: 一种通过与载体上的多个微电子元件附着区一起形成导电再分配结构来同时制造多个微电子封装的方法。 附接区域彼此间隔开并且覆盖在载体上。 该方法还包括在相邻附接区域之间形成导电连接器元件。 每个连接器元件具有与载体相邻的第一端或第二端，并且其余端在微电子元件的高度处。 该方法还包括在连接器元件的部分上形成封装，并随后对该组件进行分组。 分为微电子单元，每个微电子单元包括微电子元件。 微电子单元的与再分布结构相对的表面具有微电子元件的有源面和连接器元件的自由端，使得两者可用于与微电子单元外部的部件连接。

公开(公告)号：US09076594B2

公开(公告)日：2015-07-07

申请号：US13797540

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01G4/06 ,  H01G4/08 ,  H01G4/01 ,  H01G4/10 ,  H01L49/02 ,  H01M4/80

CPC classification number: H01G4/33 ,  H01G4/01 ,  H01G4/08 ,  H01G4/10 ,  H01G4/385 ,  H01L28/60 ,  H01L28/92 ,  H01M4/80

Abstract: Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores.

Abstract translation: 电容器及其制造方法在此公开。 在一个实施例中，电容器包括具有第一和第二相对面的表面和多个孔，每个孔从第一表面朝向第二表面沿第一方向延伸，并且每个孔具有沿孔的壁延伸的绝缘材料 ; 第一导电部分，包括在至少一些孔内延伸的导电材料; 以及第二导电部分，其包括主要由围绕所述多个孔的单个孔的铝构成的结构的区域，所述第二导电部分通过沿着所述孔的壁延伸的绝缘材料与所述第一导电部分电隔离。

公开(公告)号：US20150145141A1

公开(公告)日：2015-05-28

申请号：US14087252

申请日：2013-11-22

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/32 ,  H01L24/33 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/08146 ,  H01L2224/0823 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/13616 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/24147 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4805 ,  H01L2224/48108 ,  H01L2224/48149 ,  H01L2224/4903 ,  H01L2224/49426 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/386 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2224/05 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/45616 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/45099

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Abstract translation: 公开了一般涉及基板的装置。 在这种装置中，第一接合通孔阵列具有从衬底的表面延伸的第一线。 第二结合通孔阵列具有从衬底的表面延伸的第二线。 通过阵列的第一结合通过阵列至少部分地设置在第二结合内。 第一结合通孔阵列的第一条导线具有第一高度。 第二接合通孔阵列的第二线具有大于用于将至少一个管芯耦合至第一接合的第一高度的第二高度，该阵列至少部分地设置在第二接合通孔阵列内。

公开(公告)号：US11270979B2

公开(公告)日：2022-03-08

申请号：US16842199

申请日：2020-04-07

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/065 ,  G06F15/78 ,  H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  G06F15/76

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.