公开(公告)号：US08893143B2

公开(公告)日：2014-11-18

申请号：US13005850

申请日：2011-01-13

Applicant: Timor Kardashov ,  Maxim Kovalenko ,  Arie Elias ,  Guy Ray

Inventor： Timor Kardashov ,  Maxim Kovalenko ,  Arie Elias ,  Guy Ray

IPC: G06F9/455 ,  G06F9/50 ,  G06F12/00 ,  G06F9/48 ,  G06F9/46 ,  G06F12/10

CPC classification number: G06F9/48 ,  G06F9/455 ,  G06F9/461 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5027 ,  G06F9/5077 ,  G06F12/1036 ,  G06F12/109 ,  G06F13/26

Abstract: Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.

Abstract translation: 公开了用于实现虚拟处理器的方法和系统。 例如，在实施例中，配置为充当多个虚拟处理器的处理装置包括包括第一程序执行存储器的第一虚拟程序空间，所述第一程序执行存储器包括运行非实时操作系统的代码 支持一个或多个非实时应用的第二虚拟程序空间，包括第二程序执行存储器的第二虚拟程序空间，所述第二程序执行存储器包括运行一个或多个实时进程的代码，以及中央处理单元（CPU ），其被配置为在第一操作模式和第二操作模式下操作，所述CPU被配置为使用所述第一操作模式的所述第一虚拟程序空间来执行操作系统和应用活动，而不使用所述第二虚拟程序空间，并且不明显地干扰 在第二操作模式下运行的一个或多个实时进程。

公开(公告)号：US08866831B2

公开(公告)日：2014-10-21

申请号：US14172493

申请日：2014-02-04

Applicant: Intel Corporation

Inventor： Boris Ginzburg

IPC: G06F15/167 ,  G06F15/16 ,  G09G5/39 ,  G06F12/12 ,  G06T1/60 ,  G06F12/10 ,  G06F3/14 ,  G09G5/36

CPC classification number: G06T1/60 ,  G06F3/14 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/656 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

公开(公告)号：US08725941B1

公开(公告)日：2014-05-13

申请号：US13267736

申请日：2011-10-06

Applicant: Ran Gilboa ,  Barry S. Kleinman ,  Anton Sergeev

Inventor： Ran Gilboa ,  Barry S. Kleinman ,  Anton Sergeev

IPC: G06F12/08 ,  G06F12/10 ,  G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0646 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0689 ,  G06F11/3409 ,  G06F11/3442 ,  G06F11/3485 ,  G06F12/08 ,  G06F12/0833 ,  G06F12/1036 ,  G06F2201/815

Abstract: A virtualized storage system comprises at least one host, at least one virtual array, a backend array and a management server. The host requests storage operations to the virtual array, and the virtual array executes storage operations for the host. The backend array, coupled to the virtual array, comprises physical storage for the virtual array. The management server determines the efficiency for the virtual array. The management server determines an input throughput data rate between the host and the virtual array based on storage operations between host and virtual array. The management server also determines an output throughput data rate, from the virtual array to the backend array. The output throughput data rate is based on the storage operations that require access to the backend array. The management server determines the efficiency of the virtual array using the input throughput data rate and the output throughput data rate.

Abstract translation: 虚拟化存储系统包括至少一个主机，至少一个虚拟阵列，后端阵列和管理服务器。 主机向虚拟阵列请求存储操作，虚拟阵列执行主机的存储操作。 耦合到虚拟阵列的后端阵列包括虚拟阵列的物理存储。 管理服务器确定虚拟阵列的效率。 管理服务器根据主机和虚拟阵列之间的存储操作确定主机与虚拟阵列之间的输入吞吐量数据速率。 管理服务器还确定从虚拟阵列到后端阵列的输出吞吐量数据速率。 输出吞吐量数据速率基于需要访问后端阵列的存储操作。 管理服务器使用输入吞吐量数据速率和输出吞吐量数据速率来确定虚拟阵列的效率。

公开(公告)号：US08719547B2

公开(公告)日：2014-05-06

申请号：US12562477

申请日：2009-09-18

Applicant: Gautham N. Chinya ,  Hong Wang ,  Deepak A. Mathaikutty ,  Jamison D. Collins ,  Ethan Schuchman ,  James P. Held ,  Ajay V. Bhatt ,  Prashant Sethi ,  Stephen F. Whalley

Inventor： Gautham N. Chinya ,  Hong Wang ,  Deepak A. Mathaikutty ,  Jamison D. Collins ,  Ethan Schuchman ,  James P. Held ,  Ajay V. Bhatt ,  Prashant Sethi ,  Stephen F. Whalley

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/254

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程 记忆。 以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。 描述和要求保护其他实施例。

公开(公告)号：US20140101361A1

公开(公告)日：2014-04-10

申请号：US13646779

申请日：2012-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORP

Inventor： Michael K. Gschwind

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0671 ,  G06F3/0673 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/0292 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/657 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.

Abstract translation: 系统配置提供有多个分区，支持不同类型的地址转换结构格式。 该配置可以包括使用单个级别的翻译的分区和使用嵌套翻译级别的分区。 此外，可以使用不同类型的翻译结构。 不同的分区由单个管理程序支持。

公开(公告)号：US08688432B2

公开(公告)日：2014-04-01

申请号：US12259891

申请日：2008-10-28

Applicant: Ahmed Gheith ,  Hua Yong Wang ,  Kun Wang ,  Yu Zhang

Inventor： Ahmed Gheith ,  Hua Yong Wang ,  Kun Wang ,  Yu Zhang

IPC: G06F9/455

CPC classification number: G06F9/45537 ,  G06F12/0223 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/151

Abstract: A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system.

Abstract translation: 一种用于通过主机系统上的直接地址映射来加速存储器管理单元仿真的方法，装置和全系统模拟器，所述主机系统支持模拟客机系统的全系统模拟器，所述方法包括以下步骤： 在由主机系统分配给全系统模拟器的逻辑空间中设置边界，从而将逻辑空间划分为安全区域和模拟器占用区域; 将全系统仿真器本身从占用的原始主机逻辑空间转移到模拟器占用区域; 并保留与客户系统的至少一部分一起使用的安全区域。

公开(公告)号：US08669992B2

公开(公告)日：2014-03-11

申请号：US13895723

申请日：2013-05-16

Applicant: Intel Corporation

Inventor： Boris Ginzburg

IPC: G06F15/167 ,  G06F15/16

CPC classification number: G06T1/60 ,  G06F3/14 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/656 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有设备处理器和设备存储器的设备。 该设备可以连接到具有主机处理器和主机内存的主机。 两个存储器都可以具有页表以将虚拟地址映射到相应存储器的物理地址，并且两个存储器可以以用户级应用程序显示为单个虚拟存储器空间。 描述和要求保护其他实施例。

公开(公告)号：US20140068137A1

公开(公告)日：2014-03-06

申请号：US13597575

申请日：2012-08-29

Applicant: Andrew G. Kegel ,  Mark D. Hummel

Inventor： Andrew G. Kegel ,  Mark D. Hummel

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1036 ,  G06F12/1081 ,  G06F12/109

Abstract: A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device. The virtual IOMMU uses data structures including a guest page table, a host page table and a general control register (i.e., GCR3) table. The guest page table is implemented in hardware to support the speed requirements of the virtual IOMMU. The GCR3 table is indexed using a virtual DeviceID parameter stored in a device table.

Abstract translation: 虚拟输入/输出存储器管理单元（IOMMU）被配置为围绕与输入/输出（I / O）设备相关联的存储器请求提供防火墙。 虚拟IOMMU使用包括访客页表，主页表和通用控制寄存器（即，GCR3）表的数据结构。 来宾页表以硬件实现，以支持虚拟IOMMU的速度要求。 使用设备表中存储的虚拟DeviceID参数对GCR3表进行索引。

公开(公告)号：US20140059547A1

公开(公告)日：2014-02-27

申请号：US14072855

申请日：2013-11-06

Applicant: Yun Wang ,  Yaozu Dong

Inventor： Yun Wang ,  Yaozu Dong

IPC: G06F9/455

CPC classification number: G06F9/45545 ,  G06F9/45554 ,  G06F9/45558 ,  G06F9/5077 ,  G06F12/0246 ,  G06F12/1036 ,  G06F12/109

Abstract: Machine-readable media, methods, apparatus and system are described. In some embodiments, a virtual machine monitor of a computer platform may comprise a service virtual machine created by the virtual machine monitor partitioning an underlying hardware machine to support execution of a plurality of overlying guest operating systems, wherein the plurality of guest operating systems comprise a guest operating system complying with a non-native guest system architecture different from a host system architecture with which the hardware machine complies. The service virtual machine may further comprise a translation layer to translate instructions from the guest operating system complying with the non-native guest system architecture into instructions complying with the host system architecture.

Abstract translation: 描述了机器可读介质，方法，装置和系统。 在一些实施例中，计算机平台的虚拟机监视器可以包括由虚拟机监视器创建的服务虚拟机，该虚拟机监视器划分底层硬件机器以支持多个重叠的客户操作系统的执行，其中多个客户操作系统包括 符合非本地客户机系统架构的客户机操作系统与硬件机器符合的主机系统架构不同。 服务虚拟机还可以包括翻译层，以将符合非本地客户系统体系结构的来宾操作系统的指令转换为符合主机系统体系结构的指令。

公开(公告)号：US20140052956A1

公开(公告)日：2014-02-20

申请号：US13969562

申请日：2013-08-17

Applicant: Laurent MOLL

Inventor： Laurent MOLL

IPC: G06F12/02

CPC classification number: G06F12/1036 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1081 ,  G06F17/5009 ,  G06F2212/681

Abstract: A multi-dimension engine, connected to a system TLB, generates sequences of addresses to request page address translation prefetch requests in advance of predictable accesses to elements within data arrays. Prefetch requests are filtered to avoid redundant requests of translations to the same page. Prefetch requests run ahead of data accesses but are tethered to within a reasonable range. The number of pending prefetches are limited. A system TLB stores a number of translations, the number being relative to the dimensions of the range of elements accessed from within the data array.

Abstract translation: 连接到系统TLB的多维引擎在对数据阵列内的元素的可预测访问之前产生地址序列以请求页面地址转换预取请求。 预取提取请求被过滤以避免翻译到同一页面的冗余请求。 预取请求在数据访问之前运行，但系在一个合理的范围内。 待处理的预取数量有限。 系统TLB存储多个翻译，该数字相对于从数据阵列内访问的元素的范围的维数而言。