公开(公告)号：US07480329B2

公开(公告)日：2009-01-20

申请号：US10978103

申请日：2004-10-29

Applicant: Steven D. Draving ,  Allen Montijo

Inventor： Steven D. Draving ,  Allen Montijo

IPC: H04B3/46

CPC classification number: H04L1/205

Abstract: Separation and analysis of measured Total Jitter (TJ) begins with a suitably long arbitrary digital test pattern, from which an Acquisition Record is made. A Time Interval Error (TIE) or Voltage Level Error (VLE) Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and has associated therewith a collection of Descriptors and their respective Metrics. Each Descriptor identifies one of the various different patterns of bit value or transitions that fit the Template. The TIE/VLE Record is examined, and a parameter is measured for each instance of each Descriptor for the Template. The collection of measured parameters for each particular Descriptor are combined (e.g., averaging) to produce the Metric for that Descriptor. A Look-Up Table (LUT) addressed by the different possible Descriptors is loaded with the associated discovered Metric, which is a plausible value for Data Dependent Jitter (DDJ) at that bit. DDJ separates from TJ because DDJ is correlated with the Descriptors, while Periodic Jitter (PJ) and Random Jitter (RJ) can be expected to average to near zero over a sufficient number of instances of a given Descriptor. Identified instances of DDJ are individually removed from corresponding locations of TJ found for the entire waveform (the original TIE/VLE Record) to leave an Adjusted TIE/VLE Record that is PJ convolved with RJ.

Abstract translation: 测量的总抖动（TJ）的分离和分析开始于适当长度的任意数字测试模式，从中进行采集记录。 时间间隔误差（TIE）或电压电平误差（VLE）记录由采集记录组成。 模板定义了与感兴趣的位位置相邻或相关的关联位值或转换的集合，并且与其相关联的描述符及其各自度量的集合。 每个描述符标识适合模板的各种不同模式的位值或转换。 检查TIE / VLE记录，并为模板的每个描述符的每个实例测量一个参数。 将每个特定描述符的测量参数的集合组合（例如，平均）以产生该描述符的度量。 由不同的可能描述符寻址的查找表（LUT）被加载有相关联的发现的度量，这是该比特处的数据依赖抖动（DDJ）的合理值。 DDJ与TJ分离，因为DDJ与描述符相关，而在给定描述符的足够数量的情况下，期望抖动（PJ）和随机抖动（RJ）可以平均接近零。 DDJ的识别实例从整个波形（原始TIE / VLE记录）中找到的TJ的相应位置被单独删除，以保留与RJ卷积的PJ调整的TIE / VLE记录。

公开(公告)号：US07463578B2

公开(公告)日：2008-12-09

申请号：US10571335

申请日：2003-09-10

Applicant: Naoto Iwamura ,  Seiichi Yamaguchi ,  Yasushi Miyagawa ,  Shinya Hatakeyama

Inventor： Naoto Iwamura ,  Seiichi Yamaguchi ,  Yasushi Miyagawa ,  Shinya Hatakeyama

IPC: G01R3/08 ,  G06F11/00 ,  G08C15/04 ,  H04J1/16 ,  H04J3/14

CPC classification number: H04W28/18 ,  H04L1/0001 ,  H04L1/0009 ,  H04L1/0026 ,  H04L1/1867 ,  H04L1/205 ,  H04L29/06027 ,  H04L47/10 ,  H04L47/14 ,  H04L47/2416 ,  H04L47/2458 ,  H04L47/25 ,  H04L47/283 ,  H04L65/608 ,  H04L65/80

Abstract: A transmission parameter control apparatus that improves transmission quality of real-time media in a transmission route that includes a wireless section in at least a part of the transmission route. The transmission parameter control apparatus is connected to a terminal via a network and is connected to a mobile terminal via a wireless link. The apparatus includes: an obtaining part for obtaining a quality parameter indicating transmission quality corresponding to the wireless link from signals of downlink and uplink transmission routes; and an adjustment part for adjusting a value of a transmission parameter determining a transmission scheme in the wireless link according to the quality parameter.

Abstract translation: 一种传输参数控制装置，其改善包括至少部分传输路由中的无线部分的传输路由中的实时媒体的传输质量。 传输参数控制装置经由网络连接到终端，并通过无线链路连接到移动终端。 该装置包括：获取部分，用于从下行链路和上行链路传输路由的信号获得指示与无线链路相对应的传输质量的质量参数; 以及调整部件，用于根据质量参数来调整确定无线链路中的传输方案的传输参数的值。

公开(公告)号：US20080276001A1

公开(公告)日：2008-11-06

申请号：US11743565

申请日：2007-05-02

Applicant: Jyotikumar Menon

Inventor： Jyotikumar Menon

IPC: G06F15/16

CPC classification number: H04L1/205 ,  H04L1/203 ,  H04L41/508 ,  H04L43/0829 ,  H04L43/087 ,  H04L47/10 ,  H04L65/80

Abstract: A method, system and computer program product for calculating a scaled quality indicator expressing a quality of experience for streaming media, includes calculating network characteristics of packet loss rate of the streaming media, calculating network characteristics of packet jitter of the streaming media, and calculating the scaled quality indicator based on the calculated packet loss rate and the calculated packet jitter.

Abstract translation: 一种用于计算表示流媒体体验质量的缩放质量指标的方法，系统和计算机程序产品，包括计算流媒体的分组丢失率的网络特性，计算流媒体的分组抖动的网络特性，以及计算 基于计算出的丢包率和计算的数据包抖动的缩放质量指标。

公开(公告)号：US07439724B2

公开(公告)日：2008-10-21

申请号：US10638825

申请日：2003-08-11

Applicant: David F. Heidel ,  Keith A. Jenkins

Inventor： David F. Heidel ,  Keith A. Jenkins

IPC: G01R23/00 ,  H04L7/00 ,  H03L7/06

CPC classification number: H04L1/205 ,  G01R29/26 ,  G01R31/3016 ,  G01R31/31709 ,  G01R31/31725

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract translation: 提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链 用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟 的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。

公开(公告)号：US07428717B1

公开(公告)日：2008-09-23

申请号：US11343415

申请日：2006-01-30

Applicant: Anthony T. Duong

Inventor： Anthony T. Duong

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5054 ,  G01R31/31709 ,  H04L1/205

Abstract: An integrated software tool for system noise management is described. A system noise management suite for an assembly includes an integrated circuit design to be coupled to a circuit board design. The system includes three modules and a user interface. The first module is configured to determine at least one type of bounce voltage for the assembly. The second module is configured to identify decoupling capacitances for the assembly to reduce power distribution system noise. The third module is configured to estimate jitter caused by the integrated circuit design. The user interface is coupled to the first module, the second module, and the third module for input of information for the first module, the second module, and the third module.

Abstract translation: 描述了用于系统噪声管理的集成软件工具。 用于组件的系统噪声管理套件包括要耦合到电路板设计的集成电路设计。 该系统包括三个模块和一个用户界面。 第一模块被配置为确定组件的至少一种类型的反弹电压。 第二模块被配置为识别组件的去耦电容以减少配电系统噪声。 第三模块被配置为估计由集成电路设计引起的抖动。 用户接口耦合到第一模块，第二模块和第三模块，用于输入第一模块，第二模块和第三模块的信息。

公开(公告)号：US07383160B1

公开(公告)日：2008-06-03

申请号：US11427860

申请日：2006-06-30

Applicant: Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

Inventor： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

IPC: G06F19/00

CPC classification number: H04L1/205 ,  G01R31/31709

Abstract: A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.

Abstract translation: 一种用于提供信号图的低成本和生产可集成技术的方法。 数据信号被边缘检测和异步采样（或者时钟信号被锁存）。 将数据信号或第二信号与可设置的阈值电压进行比较并采样。 边缘和比较数据根据扫描时基折叠以找到最小抖动周期。 信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。 对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。 该技术在可设置的阈值电压范围内重复。 然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。

公开(公告)号：US20080107221A1

公开(公告)日：2008-05-08

申请号：US11932956

申请日：2007-10-31

Applicant: Shigeyuki YAMANAKA ,  Yusuke YAMADA

Inventor： Shigeyuki YAMANAKA ,  Yusuke YAMADA

IPC: H04L7/00

CPC classification number: H04L1/0001 ,  H04L1/0002 ,  H04L1/0009 ,  H04L1/18 ,  H04L1/1825 ,  H04L1/205

Abstract: A packet is transmitted such that jitter of a packet transmission time period is suppressed. A transmission apparatus includes a stream data obtaining unit obtaining stream data from a source outside of the transmission apparatus, a coding unit compressing and coding the stream data, a packet generation unit generating a packet, a transmission buffer unit temporarily storing data, a transmission method selection unit selecting any one of “jitter suppressed transmission” and “normal transmission” as a transmission mode, a communication I/F unit transmitting the packetized stream data with a transmission method selected by the transmission method selection unit, a communication medium detection unit obtaining data for controlling communication via the communication I/F unit by identifying a communication medium, a time keeping unit generating time information, an input unit accepting manipulation input, and a storage unit storing data in a non-volatile manner.

Abstract translation: 发送分组，使得分组传输时间段的抖动被抑制。 发送装置包括流数据获取单元，从发送装置外的源获取流数据，对流数据进行压缩编码的编码单元，生成分组的分组生成单元，临时存储数据的发送缓冲单元，发送方法 选择单元选择“抖动抑制发送”和“正常发送”中的任一个作为发送模式，通信I / F单元以由发送方式选择单元选择的发送方式发送分组化流数据，通信介质检测单元获取 用于通过识别通信介质来控制经由通信I / F单元的通信的数据，产生时间信息的时间保持单元，接受操作输入的输入单元和以非易失性方式存储数据的存储单元。

公开(公告)号：US07356109B2

公开(公告)日：2008-04-08

申请号：US11585526

申请日：2006-10-23

Applicant: Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

Inventor： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC: H04L7/00

CPC classification number: G01R31/31709 ,  G01R31/31725 ,  G01R31/31922 ,  G01R31/31937 ,  H04L1/205

Abstract: Timing jitter sequences Δφj[n] and Δφk[n] of respective clock signals under measurement xj(t) and xk(t) are estimated, and a timing difference sequence between those timing jitter sequences is calculated. In addition, initial phase angles φ0j and φ0k of linear instantaneous phases of the xj(t) and xk(t) are estimated, respectively. A sum of a difference between those initial angles and the timing difference sequence is calculated to obtain a clock skew sequence between the xj(t) and xk(t).

Abstract translation: （t）和x k（t），并且计算那些定时抖动序列之间的定时差异序列。 另外，x 0 和＆lt; 0＆lt; 0＆gt; （t）和x（k）分别被估计。 计算出这些初始角度和定时差分序列之间的差值的和，以获得x j（t）和x k（t）之间的时钟偏移序列。

公开(公告)号：US07339984B1

公开(公告)日：2008-03-04

申请号：US10656929

申请日：2003-09-05

Applicant: Fadi Daou

Inventor： Fadi Daou

IPC: H04B17/00

CPC classification number: H04L1/205 ,  H03L7/18 ,  H04L7/033 ,  H04L7/0334

Abstract: An apparatus and method for measuring jitter using phase and amplitude undersampling. A sampling circuit samples an input signal to obtain amplitude and phase information, a computation circuit determines Time Interval Error (TIE) information from the amplitude and phase information, and a signal processor processes the TIE information to generate a jitter spectrum.

Abstract translation: 一种使用相位和幅度欠采样来测量抖动的装置和方法。 采样电路对输入信号进行采样以获得幅度和相位信息，计算电路根据振幅和相位信息确定时间间隔误差（TIE）信息，并且信号处理器处理TIE信息以产生抖动频谱。

公开(公告)号：US07321612B2

公开(公告)日：2008-01-22

申请号：US10418035

申请日：2003-04-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04B1/38

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 时钟和数据恢复电路具有可调节的锁相环（PLL）带宽，其被设置为对应于服务的高速比特流的抖动带宽。