公开(公告)号：US07470554B2

公开(公告)日：2008-12-30

申请号：US11212639

申请日：2005-08-29

Applicant: Toru Sugeno

Inventor： Toru Sugeno

IPC: H01L21/469 ,  H01C7/00 ,  B05D3/02 ,  H01L29/06

CPC classification number: H01L51/0021 ,  H01L21/76801 ,  H01L27/3244 ,  H05K1/092 ,  H05K3/02 ,  H05K3/1291 ,  H05K3/28 ,  H05K2201/017 ,  H05K2203/0514 ,  H05K2203/1126

Abstract: A method of forming a stacking structure by forming an electroconductive layer precursor pattern by an electroconductive paste made of a resin component, electroconductive fine particles, and glass fine particles, forming a dielectric layer precursor pattern by a dielectric paste made of a resin component and glass fine particles, and simultaneously baking both of those patterns, wherein they are held for a predetermined time while keeping a baking temperature which is equal to or higher than a decomposing temperature of the resin component and is equal to or lower than a baking start temperature of the glass fine particles and, thereafter, their baking is completed at the baking temperature which is equal to or higher than the baking start temperature of the glass fine particles and is lower than its softening point. Thus, the occurrence of a void and a pin hole in an insulative layer can be prevented in the stacking structure after the baking.

Abstract translation: 通过使用由树脂成分，导电性微粒和玻璃微粒构成的导电性浆料形成导电性前体图形而形成层叠结构体的方法，通过树脂成分制成的电介质膏和玻璃形成电介质层前体图案 并且同时烘烤这些图案，其中它们保持预定时间，同时保持等于或高于树脂成分的分解温度的烘烤温度，并且等于或低于烘烤开始温度 然后在等于或高于玻璃微粒的烘焙开始温度并且低于其软化点的烘烤温度下完成其烘烤。 因此，可以防止在烘烤后的堆叠结构中发生绝缘层中的空隙和针孔。

公开(公告)号：US20080152928A1

公开(公告)日：2008-06-26

申请号：US12000177

申请日：2007-12-10

Applicant: Yasuharu Miyauchi ,  Toshiyuki Suzuki ,  Masaharu Hirakawa ,  Tomoko Nakamura ,  Toshinobu Miyakoshi ,  Kiyoshi Hatanaka

Inventor： Yasuharu Miyauchi ,  Toshiyuki Suzuki ,  Masaharu Hirakawa ,  Tomoko Nakamura ,  Toshinobu Miyakoshi ,  Kiyoshi Hatanaka

IPC: B32B17/06

CPC classification number: H05K3/38 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2203/1163 ,  H05K2203/308 ,  Y10T428/31678 ,  H01L2924/00

Abstract: A highly reliable ceramics substrate which can sufficiently secure a bonding strength of a surface conductor in an initial state and after a lapse of time (e.g., after a PCT) is provided. The multilayer ceramics substrate has a surface conductor on at least one surface of a multilayer body constituted by a plurality of laminated ceramics substrate layers. A reaction phase formed by a reaction between a ceramics component in the ceramics substrate layers and a glass component in the surface conductor is deposited at an interface between the surface conductor and ceramics substrate layers. For example, an alumina filler in the ceramics substrate layers and Zn in the surface conductor react with each other, thereby forming ZnAl2O4 as the reaction phase.

Abstract translation: 提供了一种高度可靠的陶瓷基板，其能够充分确保初始状态下和经过时间（例如，PCT之后）的表面导体的结合强度。 多层陶瓷基板在由多层叠陶瓷基板层构成的多层体的至少一个面上具有表面导体。 通过陶瓷基板层中的陶瓷部件与表面导体中的玻璃成分之间的反应形成的反应相沉积在表面导体与陶瓷基板层之间的界面处。 例如，陶瓷基体层中的氧化铝填料和表面导体中的Zn彼此反应，从而形成作为反应相的ZnAl 2 O 4 O 4。

公开(公告)号：US20080035943A1

公开(公告)日：2008-02-14

申请号：US11891366

申请日：2007-08-10

Applicant: Joel Slutsky ,  Brian D. Veeder ,  Thomas Lin

Inventor： Joel Slutsky ,  Brian D. Veeder ,  Thomas Lin

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L21/4867 ,  H01L23/3736 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/053 ,  H05K1/092 ,  H05K3/246 ,  H05K2201/017 ,  H05K2201/0347 ,  H05K2201/10106 ,  H05K2203/0315 ,  H01L2924/00014

Abstract: The present invention provides novel methods of forming component carriers, component modules, and the carriers and modules formed therefrom which utilize thick film technology. In some embodiments, these methods are used to form lighting device chip carriers and modules. In further embodiments, these lighting device chip carriers and modules are used in LED applications.

Abstract translation: 本发明提供了形成部件载体，组件模块以及由此形成的载体和模块的新颖方法，其利用厚膜技术。 在一些实施例中，这些方法用于形成照明装置芯片载体和模块。 在另外的实施例中，这些照明装置芯片载体和模块用于LED应用中。

公开(公告)号：US20070271752A1

公开(公告)日：2007-11-29

申请号：US11891443

申请日：2007-08-10

Applicant: Cengiz Palanduz ,  Yongki Min

Inventor： Cengiz Palanduz ,  Yongki Min

IPC: H01G7/00

CPC classification number: H01G4/12 ,  H01L2224/16225 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/1131 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49155

Abstract: A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material; and sintering the ceramic material. A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material so that the ceramic material is disposed between the first conductive material and the second conductive material; thermal processing at a temperature sufficient to sinter the ceramic material and form a film of the second conductive material; and coating an exposed surface of at least one of the first conduct material and the second conductive material with a different conductive material. An apparatus including first and second electrodes; and a ceramic material between the first electrode and the second electrode, wherein the ceramic material is sintered directly on one of the first and second electrode.

Abstract translation: 一种包括在第一导电材料的片材上直接形成陶瓷材料的方法; 在所述陶瓷材料上形成第二导电材料; 并烧结陶瓷材料。 一种包括在第一导电材料的片材上直接形成陶瓷材料的方法; 在所述陶瓷材料上形成第二导电材料，使得所述陶瓷材料设置在所述第一导电材料和所述第二导电材料之间; 在足以烧结陶瓷材料并形成第二导电材料的膜的温度下进行热处理; 以及用不同的导电材料涂覆第一导电材料和第二导电材料中的至少一个的暴露表面。 一种包括第一和第二电极的装置; 以及在第一电极和第二电极之间的陶瓷材料，其中陶瓷材料直接烧结在第一和第二电极之一上。

公开(公告)号：US20070252523A1

公开(公告)日：2007-11-01

申请号：US11660476

申请日：2005-08-16

Applicant: Masakatsu Maeda ,  Yasuyuki Yamamoto

Inventor： Masakatsu Maeda ,  Yasuyuki Yamamoto

IPC: H01J1/62

CPC classification number: C04B41/009 ,  C04B41/5031 ,  C04B41/5063 ,  C04B41/5064 ,  C04B41/87 ,  C04B2111/80 ,  H01L33/60 ,  H01L33/641 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/181 ,  H05K2201/017 ,  H05K2201/10106 ,  H05K2201/2054 ,  C04B41/0072 ,  C04B41/4556 ,  C04B41/4539 ,  C04B41/5045 ,  C04B35/58 ,  C04B35/581 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A ceramic substrate for mounting a light emitting element. The ceramic substrate has a placement surface for placing a light emitting element having an electrode; and an electrode electrically-connected with the electrode of the light emitting element, wherein the ceramic substrate comprises a substrate body consisting of a nitride ceramics; and a coat layer coating at least a part of a surface of the substrate body and consisting of a ceramics different from the nitride ceramics forming the substrate body; and the coat layer has an optical reflectance of 50% or more for any light having a wavelength of from 300 to 800 nm, which can increase a luminance of the light emitting element by reflecting the light emitted from the element efficiently with certainty, and which has a high heat radiation property; and a manufacturing method therefor.

Abstract translation: 一种用于安装发光元件的陶瓷基板。 陶瓷基板具有用于放置具有电极的发光元件的放置面; 以及与所述发光元件的电极电连接的电极，其中，所述陶瓷基板包括由氮化物陶瓷构成的基板主体; 以及涂覆在所述基板主体的表面的至少一部分上并由与形成所述基板主体的所述氮化物陶瓷不同的陶瓷构成的涂层; 并且涂层对于具有300至800nm波长的任何光都具有50％或更高的光学反射率，这可以通过有效地反映从元件发射的光来增加发光元件的亮度，并且其中 具有较高的散热性能; 及其制造方法。

公开(公告)号：US20070139976A1

公开(公告)日：2007-06-21

申请号：US11620042

申请日：2007-01-04

Applicant: L. deRochemont

Inventor： L. deRochemont

IPC: H02M3/335

CPC classification number: H01F27/2804 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01F3/00 ,  H01F5/003 ,  H01F27/24 ,  H01F27/29 ,  H01F27/40 ,  H01F41/041 ,  H01F2027/2809 ,  H01G4/10 ,  H01G4/33 ,  H01L23/64 ,  H01L28/10 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T29/49021

Abstract: A power management module, provides an inductor including one or more electrical conductors disposed around a ferromagnetic ceramic element including one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.50 mol % throughout the ceramic element.

Abstract translation: 电源管理模块提供一种电感器，其包括设置在铁磁性陶瓷元件周围的一个或多个电导体，所述铁磁陶瓷元件包括在整个陶瓷元件中具有小于或等于1.50摩尔％的金属氧化物组成均匀性波动的一种或多种金属氧化物。

公开(公告)号：US20060282999A1

公开(公告)日：2006-12-21

申请号：US11453387

申请日：2006-06-15

Applicant: Diptarka Majumdar ,  Saul Ferguson

Inventor： Diptarka Majumdar ,  Saul Ferguson

IPC: H01G7/00 ,  H01L21/20

CPC classification number: H05K1/162 ,  H05K1/092 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/017 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2201/09909 ,  Y10T29/435 ,  Y10T29/49155

Abstract: Disclosed is an improved method of embedding capacitors in printed wiring boards (PWB) made from thick film dielectrics and electrodes.

Abstract translation: 公开了一种在由厚膜电介质和电极制成的印刷电路板（PWB）中嵌入电容器的改进方法。

公开(公告)号：US20060182939A1

公开(公告)日：2006-08-17

申请号：US11056529

申请日：2005-02-11

Applicant: Vahid Goudarzi ,  Edwin Bradley ,  Kinzy Jones ,  Gustavo Leizerovich

Inventor： Vahid Goudarzi ,  Edwin Bradley ,  Kinzy Jones ,  Gustavo Leizerovich

IPC: B32B18/00 ,  C03B29/00

CPC classification number: H05K3/3452 ,  B32B18/00 ,  C04B2237/32 ,  C04B2237/592 ,  C04B2237/62 ,  C04B2237/68 ,  H01C1/144 ,  H01G4/232 ,  H01G4/236 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  Y10T29/49163 ,  Y10T428/24926

Abstract: A method (50) of forming a solder mask on a portion of a module (40) using for example LTCC technology includes the steps of forming (52) a multilayered ceramic substrate (20) with exposed metallization forming solder pads (28 or 31), masking (54 or 56) the solder pads by placing an additional ceramic layer (22 or 32) on the substrate that at least covers at least a portion of periphery of the solder pad using the LTCC process. The method can further include applying (58 or 60) solder (36) to a portion of the solder pad not covered by the solder mask (22) and placing a printed circuit board (34) having a different coefficient of thermal expansion than the multilayer ceramic substrate on the multilayer ceramic substrate to form the module before reflowing. The module can then be reflowed to form the module without cracks.

Abstract translation: 使用例如LTCC技术在模块（40）的一部分上形成焊料掩模的方法（50）包括以下步骤：用暴露的金属化形成焊盘（28或31）形成（52）多层陶瓷衬底（20） 通过在衬底上放置另外的陶瓷层（22或32）来掩模（54或56）焊盘，该陶瓷层至少覆盖焊料垫的至少一部分，使用LTCC工艺。 该方法还可以包括将（58或60）焊料（36）施加到未被焊料掩模（22）覆盖的焊料焊盘的一部分，并且放置具有与多层不同的热膨胀系数不同的印刷电路板（34） 陶瓷基板在多层陶瓷基板上形成回流模块。 然后可以将模块回流以形成模块而没有裂缝。

公开(公告)号：US20030227083A1

公开(公告)日：2003-12-11

申请号：US10453503

申请日：2003-06-04

Inventor： Jin Hyung Ryu ,  Sam Je Cho

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H05K3/3452 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package and method for package a semiconductor that has high reliability. A semiconductor package according to the present invention comprises a first substrate on which a circuit pattern and an electrode pad are formed; a second substrate which is adhered to the first substrate and on which a hole is formed; and a solder ball adhered to the electrode pad through the hole formed on the second substrate. Then, the second substrate is used as a solder resist. Accordingly, since the first substrate and the second substrate are formed of same material, the BGA package can be prevented from being cracked and being nonuniform when fired

Abstract translation: 公开了一种具有高可靠性的用于封装半导体的半导体封装和方法。 根据本发明的半导体封装包括其上形成有电路图案和电极焊盘的第一基板; 第二基板，其粘附到所述第一基板并且在其上形成有孔; 并且焊球通过形成在第二基板上的孔粘附到电极焊盘。 然后，将第二基板用作阻焊剂。 因此，由于第一基板和第二基板由相同的材料形成，因此可以防止BGA封装在被烧断时发生裂纹和不均匀

公开(公告)号：US20030011999A1

公开(公告)日：2003-01-16

申请号：US09789454

申请日：2001-02-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jun Urakawa ,  Mitsuyoshi Nishide ,  Isao Kato ,  Norio Yoshida ,  Tomonori Ito

IPC: H05K007/00

CPC classification number: H01L24/16 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K3/3452 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2201/09909 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A ceramic multi-layer wiring substrate includes a line-shaped insulation pattern arranged to extend over a plurality of surface wiring patterns and to intersect the respective surface wiring patterns, in which soldering land electrodes are defined by the insulation patterns.

Abstract translation: 陶瓷多层布线基板包括布置成在多个表面布线图案上延伸并且与相应的表面布线图案相交的线状绝缘图案，其中焊接电极由绝缘图案限定。