公开(公告)号：US20080290495A1

公开(公告)日：2008-11-27

申请号：US12068606

申请日：2008-02-08

Applicant: Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

Inventor： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

IPC: H01L23/528

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract translation: 作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持 阻抗低在低频。

公开(公告)号：US20080264679A1

公开(公告)日：2008-10-30

申请号：US11720448

申请日：2004-11-30

Applicant: Johan Sandwall

Inventor： Johan Sandwall

IPC: H05K1/03

CPC classification number: H05K1/024 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0391 ,  H05K2201/09972 ,  H05K2203/061

Abstract: The invention discloses a PCB (100, 400) with first and second main surfaces (110, 130), the PCB also having a first height, h, said two surfaces and height together defining the volume of the PCB. The PCB comprises layers (430, 434, 438) of a first supporting laminate material, layers (440, 431, 433, 435, 437, 439) of a first conducting material and layers (432, 436) of a first prepreg, said first materials and prepreg having respective dielectrical constants and dissipation factors. In the PCB, a sub-volume of the PCB defined by a sub-area (120) within the first main surface and a sub-height (h′) within said first height together comprise a sub-PCB (320) which comprises at least one layer (330, 334) of a second supporting laminate material, said second laminate material differing from the first laminate material with regard to at least one of the factors dielectrical constant and dissipation factor.

Abstract translation: 本发明公开了一种具有第一和第二主表面（110,130）的PCB（100,400），PCB还具有第一高度h，所述两个表面和高度一起限定PCB的体积。 PCB包括第一支撑层叠材料的层（430,434,438），第一导电材料的层（440,431,433,435,437,439）和第一半固化片的层（432,436），所述层 第一材料和预浸料具有各自的介电常数和耗散因子。 在PCB中，由第一主表面内的子区域（120）限定的PCB的子体积和所述第一高度内的子高度（h'）一起包括子PCB（320），其包括在 至少一层（330,334）的第二支撑层压材料，所述第二层压材料与第一层压材料不同于至少一个因素介电常数和耗散因子。

公开(公告)号：US20080241359A1

公开(公告)日：2008-10-02

申请号：US11730212

申请日：2007-03-30

Applicant: Norman A. Card ,  Robert J. Harendza ,  John J. Konrad ,  Tonya Mosher ,  Susan Pitely ,  Jose A. Rios

Inventor： Norman A. Card ,  Robert J. Harendza ,  John J. Konrad ,  Tonya Mosher ,  Susan Pitely ,  Jose A. Rios

IPC: H01C17/06

CPC classification number: H01C17/065 ,  H01C1/144 ,  H01C7/006 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3468 ,  H05K2201/0391 ,  H05K2203/044 ,  H05K2203/0574 ,  H05K2203/0577

Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.

Abstract translation: 一种制造电路化衬底的方法，其中导体以这样的方式形成，使得所选择的导体包括焊料，而另一些导体不适于接收不同于覆盖的焊料的不同形式的连接（例如，引线接合） 导体 在一个实施例中，焊料可以通过将衬底浸入焊料槽中而以熔融形式施加，而在另一种焊料中可以使用筛选程序进行沉积。

公开(公告)号：US07321172B2

公开(公告)日：2008-01-22

申请号：US11227532

申请日：2005-09-14

Applicant: Dustin P. Wood ,  Debendra Mallik

Inventor： Dustin P. Wood ,  Debendra Mallik

IPC: H01L23/48

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

Abstract: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

Abstract translation: 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US07163613B2

公开(公告)日：2007-01-16

申请号：US10923874

申请日：2004-08-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: C25D5/16 ,  C25D5/02 ,  C25D5/00 ,  C25D7/06

CPC classification number: H01L24/86 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/242 ,  H05K3/243 ,  H05K3/323 ,  H05K3/422 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0394 ,  H05K2203/049 ,  H05K2203/072 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K2203/1545 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.

Abstract translation: 提供了一种半导体器件，包括：形成在互连图案的一个表面上的第一镀层; 形成在所述互连图案中的通孔内的第二镀层; 电连接到第一镀层的半导体芯片; 设置在第一镀层上的各向异性导电材料; 以及设置在所述第二镀层上的导电材料，其中所述第一镀层与所述各向异性导电材料具有适当的粘合性，并且所述第二镀层与所述导电材料具有适当的粘合性能。

公开(公告)号：US20060280918A1

公开(公告)日：2006-12-14

申请号：US11412266

申请日：2006-04-26

Applicant: Shinji Murata

Inventor： Shinji Murata

IPC: B32B3/00

CPC classification number: H05K3/248 ,  H01L2224/73204 ,  H05K1/0306 ,  H05K1/09 ,  H05K1/092 ,  H05K1/111 ,  H05K2201/0391 ,  Y10T428/12028 ,  Y10T428/12868 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: Provided is a wiring portion capable of suppressing diffusion from occurring in a wiring portion or between the wiring portion and a substrate. In the wiring substrate, a first high melting point metal portion 18 having a melting point higher than Au and Ag is provided between an Au wiring portion 15 and an Ag wiring portion 17. The higher the melting point of the first high melting point metal portion 18, the lower a coefficient thereof, that is, the harder diffusion occurs. In addition, the first high melting point metal portion 19 functions as a barrier material which adequately suppresses Ag from being diffused from the Ag wiring portion 17. By providing the first high melting point metal portion 18 between the Au wiring portion 15 and the Ag wiring portion 17, it is possible to more efficiently suppress Ag from diffusion, in comparison with a case where the Ag wiring portion and the Au wiring portion are in contact with each other.

Abstract translation: 提供一种能够抑制在布线部分或布线部分和基板之间发生扩散的布线部分。 在布线基板中，在Au布线部分15和Ag布线部分17之间设置熔点高于Au和Ag的第一高熔点金属部分18。 第一高熔点金属部分18的熔点越高，其系数越低，即发生较硬的扩散。 此外，第一高熔点金属部分19用作阻挡材料，其充分地抑制Ag从Ag布线部分17扩散。 通过在Au布线部分15和Ag布线部分17之间设置第一高熔点金属部分18，与Ag布线部分和Au布线部分是相同的情况相比，可以更有效地抑制Ag扩散。 彼此接触。

公开(公告)号：US20060099727A1

公开(公告)日：2006-05-11

申请号：US10968929

申请日：2004-10-21

Applicant: John Konrad ,  Joseph Kotylo ,  Jose Rios

Inventor： John Konrad ,  Joseph Kotylo ,  Jose Rios

IPC: H01L21/66

CPC classification number: H01L21/486 ,  H05K3/243 ,  H05K3/3463 ,  H05K3/3473 ,  H05K3/42 ,  H05K2201/0391 ,  H05K2203/0542 ,  H05K2203/0723

Abstract: A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.

公开(公告)号：US20040242086A1

公开(公告)日：2004-12-02

申请号：US10796983

申请日：2004-03-11

Applicant: AUTONETWORKS TECHNOLOGIES, LTD. ,  SUMITOMO WIRING SYSTEMS, LTD. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Kouichi Takagi

IPC: H01R004/48

CPC classification number: H05K3/202 ,  H05K1/029 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/10166 ,  H05K2203/175

Abstract: An integrated bus bar structure plate in which a plurality of bus bars are arranged on substantially the one plain face to form an electric power circuit, wherein after the bus bar structure plate having a whole shape in which a plurality of types of electric power circuits are formed by selecting any of the connection parts of the bus bars is separated is adhered to the control circuit board whereby, for example, a desired electric power circuit is formed among the connection parts of bus bars.

Abstract translation: 一种集成汇流条结构板，其中多个汇流条布置在基本上一个平面上以形成电力电路，其中在具有整体形状的汇流条结构板之后，多个类型的电力电路是 通过选择母线的任何一个连接部分形成的分离的部分粘附到控制电路板，由此例如在汇流条的连接部分之间形成期望的电力电路。

公开(公告)号：US20040184244A1

公开(公告)日：2004-09-23

申请号：US10800677

申请日：2004-03-16

Applicant: YAZAKI CORPORATION

Inventor： Koichi Uezono

IPC: H05K007/02

CPC classification number: B60R16/0238 ,  H05K1/0263 ,  H05K3/103 ,  H05K7/026 ,  H05K2201/0391 ,  H05K2201/09845 ,  H05K2201/09972 ,  H05K2201/10272 ,  H05K2201/10287

Abstract: A first board, on which electric wires are wired, includes a first part having a first thickness and a second part continued from the first part and having a second thickness smaller than the first thickness. A second board, on which bus bars are arranged, is disposed on the second part of the first board. The second board has a third thickness which is determined such that an additional thickness of the second thickness and the third thickness is not greater than the first thickness.

Abstract translation: 电线布线在其上的第一板包括具有第一厚度的第一部分和从第一部分延续的第二部分，并且具有小于第一厚度的第二厚度。 布置有母线的第二板被布置在第一板的第二部分上。 第二板具有第三厚度，其被确定为使得第二厚度和第三厚度的附加厚度不大于第一厚度。

公开(公告)号：US20030180510A1

公开(公告)日：2003-09-25

申请号：US10357183

申请日：2003-02-03

Inventor： Minoru Ogawa ,  Masahiro Izumi ,  Shigeyasu Itoh ,  Shingetsu Yamada ,  Shuuji Suzuki ,  Hiroo Kurosaki

IPC: B32B003/00

CPC classification number: H05K3/4632 ,  H01L2224/16 ,  H01L2224/83192 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/09701 ,  H05K1/0353 ,  H05K1/0373 ,  H05K1/095 ,  H05K3/041 ,  H05K3/045 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2203/0108 ,  H05K2203/065 ,  Y02P20/582 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T428/24917 ,  Y10T428/249994

Abstract: A multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, can be ideally applied to low volume high mix manufacturing configurations, and also has little impact on the environment is provided, together with a semiconductor device mounting board using such a multilayer wiring board, and a method of manufacturing such a multilayer wiring board. In the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260null C. and an amorphous polyetherimide resin as the primary constituents, a metallic foil is embedded within the grooves so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material formed by curing a conductive paste is used for filling the via holes.

Abstract translation: 具有耐热性高的多层布线基板，其能够低温熔融而不发生树脂流动，能够实现高精度，细致的导电布线，理想地应用于低体积高混合物制造配置，并且还具有 与使用这种多层布线板的半导体装置安装板一起提供对环境的影响很小，以及制造这种多层布线板的方法。 在多层布线板中，形成布线电路和通孔的槽形成在由包含结晶熔融峰值温度至少为260℃的聚芳基酮树脂的热塑性树脂组合物形成的绝缘基板和无定形聚醚酰亚胺树脂中 主要成分，金属箔被嵌入槽内，使得箔的表面突出到绝缘基板的表面，并且通过固化导电膏形成的导电材料用于填充通孔。