公开(公告)号：US20070144773A1

公开(公告)日：2007-06-28

申请号：US11389536

申请日：2006-03-27

Applicant: Akiyoshi Saitou ,  Toru Kuraishi ,  Takeshi Midorikawa ,  Chikayuki Kumagai ,  Masashi Fujimoto

Inventor： Akiyoshi Saitou ,  Toru Kuraishi ,  Takeshi Midorikawa ,  Chikayuki Kumagai ,  Masashi Fujimoto

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/0222 ,  H01L2924/0002 ,  H05K1/113 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09809 ,  H01L2924/00

Abstract: The present invention relates to a circuit board in which signal lines transmitting a signal are wired, and which is capable of increasing the speed of signal transmission. There is provided a circuit board in which signal lines are wired, including: a signal pad which is formed at the tip of the signal line and has a signal via in the center thereof; and plural ground vias which are formed in positions to surround the signal pad and transmit a ground potential over plural wiring layers.

Abstract translation: 本发明涉及一种电路板，其中发送信号的信号线被布线，并且能够增加信号传输的速度。 提供了一种其中信号线被布线的电路板，包括：信号焊盘，其形成在信号线的尖端并且在其中心具有信号通道; 以及形成在围绕信号焊盘并在多个布线层上传输接地电位的位置的多个接地通孔。

公开(公告)号：US20070120225A1

公开(公告)日：2007-05-31

申请号：US11514097

申请日：2006-08-31

Applicant: Madhavan Swaminathan ,  Ege Engin ,  Lixi Wan ,  Prathap Muthana

Inventor： Madhavan Swaminathan ,  Ege Engin ,  Lixi Wan ,  Prathap Muthana

IPC: H01L29/93

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising using an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract translation: 本发明的一个实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括在所述封装中安装嵌入式分立陶瓷电容器阵列，以及可选的平面电容层 。 另一实施例提供了一种用于在1MHz至3GHz的中频范围内为IC提供低噪声电源封装的装置，其包括使用具有不同谐振频率的嵌入式分立陶瓷电容器阵列，其布置成使得 电容阵列的阻抗与临界中频范围内的频率曲线产生等于或低于目标阻抗值的阻抗值。

公开(公告)号：US20070108552A1

公开(公告)日：2007-05-17

申请号：US11516377

申请日：2006-09-06

Applicant: Lixi Wan

Inventor： Lixi Wan

IPC: H01L29/00

CPC classification number: H05K1/162 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/908

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract translation: 本发明公开了具有通孔连接和电极的电容器，其设计成使得它们提供低电感路径，从而减少所需的电容，同时能够使用嵌入式电容器进行功率输送和其它用途。 本发明的一个实施例公开了一种电容器，包括：顶部电容器电极和底部电容器电极，其中顶部电极小于底部电极，包括在电容器的所有侧面上; 在阵列中，位于顶部和底部电容器电极的所有侧面上的多个通孔，其中顶部电极和连接到顶部电极的通孔用作内部导体，并且底部电极和连接到底部电极的通孔 作为外部导体。

公开(公告)号：US07186924B2

公开(公告)日：2007-03-06

申请号：US10690113

申请日：2003-10-21

Applicant: Ehood Geva ,  Todd E. Takken

Inventor： Ehood Geva ,  Todd E. Takken

IPC: H05K1/00

CPC classification number: H05K1/0219 ,  H05K3/222 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/10371

Abstract: A trace cover suitable for shielding a conductive trace on a top layer of a circuit board. The trace cover includes a dielectric body disposed substantially over the conductive trace, side shielding perpendicular to the direction of the conductive trace and substantially parallel to the length of the conductive trace, and top shielding disposed on the top surface of the body. The side shielding and top shielding are electrically coupled with the at least one circuit ground of the circuit board.

Abstract translation: 适用于屏蔽电路板顶层导电迹线的痕迹盖。 迹线盖包括基本上布置在导电迹线上的绝缘体，垂直于导电迹线的方向的侧屏蔽，并且基本上平行于导电迹线的长度，以及设置在主体的顶表面上的顶部屏蔽。 侧面屏蔽和顶部屏蔽与电路板的至少一个电路接地电耦合。

公开(公告)号：US07154353B2

公开(公告)日：2006-12-26

申请号：US11043978

申请日：2005-01-28

Applicant: Hiroyuki Dohata

Inventor： Hiroyuki Dohata

IPC: H01P3/08

CPC classification number: H01P3/088 ,  H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09672

Abstract: A plurality of signal lines are provided on one main surface of a dielectric substrate. A plurality of other signal lines are provided on the other main surface of dielectric substrate. The plurality of signal lines on one main surface and the plurality of other signal lines on the other main surface are provided so as to extend in parallel to one another. A ground pattern having its potential fixed is provided between neighboring signal lines on one main surface, and a ground pattern having its potential fixed is provided between neighboring signal lines on the other surface. According to such a structure, a microstrip line that can include a larger number of signal lines on the main surfaces of the dielectric substrate, without increasing a size of the dielectric substrate is obtained.

Abstract translation: 多个信号线设置在电介质基板的一个主表面上。 在电介质基板的另一个主表面上设置多条其它信号线。 一个主表面上的多个信号线和另一个主表面上的多个其它信号线设置成彼此平行地延伸。 在一个主表面上的相邻信号线之间设置具有其电位固定的接地图案，并且在另一表面上的相邻信号线之间设置其电位固定的接地图案。 根据这种结构，可以获得在不增加电介质基板的尺寸的情况下可以在电介质基板的主表面上包含更多数量的信号线的微带线。

公开(公告)号：US07151420B2

公开(公告)日：2006-12-19

申请号：US11023879

申请日：2004-12-23

Applicant: David L. Brunker ,  Victor Zaderej

Inventor： David L. Brunker ,  Victor Zaderej

IPC: H01P3/08

CPC classification number: H05K9/0018 ,  H01P3/023 ,  H05K1/0221 ,  H05K1/024 ,  H05K3/107 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09981

Abstract: An electro-magnetically shielded slot-transmission line is formed by metallizing the opposing sides of a slot cut through a dielectric substrate. A ground plane is deposited on the bottom of the substrate. Conductive vias through the substrate and that contact the ground plane are located on both sides of the metallized slot surfaces. Conductive pads on the upper surface and which contact the vias provide additional shielding.

Abstract translation: 通过金属化通过电介质基板切割的槽的相对侧而形成电磁屏蔽槽传输线。 接地平面沉积在基底的底部。 通过基板并接触接地平面的导电孔位于金属化槽表面的两侧。 上表面上的导电焊盘与通孔接触提供额外的屏蔽。

公开(公告)号：US20060226928A1

公开(公告)日：2006-10-12

申请号：US11101882

申请日：2005-04-08

Applicant: Larry Henning ,  Lawrence Hughes ,  Karen Matthews ,  Deepukumar Nair

Inventor： Larry Henning ,  Lawrence Hughes ,  Karen Matthews ,  Deepukumar Nair

IPC: H01P5/02 ,  H01P1/00

CPC classification number: H05K1/025 ,  H01L2223/6622 ,  H01P3/06 ,  H01P5/085 ,  H05K1/0222 ,  H05K3/3436 ,  H05K2201/09618 ,  H05K2201/09809

Abstract: A pseudo-coaxial vertical transition (10) includes a substrate (16). A bump array is disposed in a substantially concentric bump pattern upon the substrate (16) for simulating a pseudo-coaxial vertical electromagnetic wave propagation. The bump array is formed from a centrally disposed bump (32) having a predetermined bump diameter, and a plurality of at least five ground bumps (36) substantially equi-distant and circularly disposed about the centrally disposed bump (32). The predetermined bump diameter and a bump spacing of the centrally disposed bump are determined in relation to the plurality of ground bumps and a dielectric constant of air for providing a characteristic impedance.

Abstract translation: 伪同轴垂直过渡（10）包括衬底（16）。 凸块阵列以基本同心的凸起图案设置在基板（16）上，用于模拟伪同轴垂直电磁波传播。 凸块阵列由具有预定凸块直径的中心设置的凸块（32）形成，并且多个至少五个接地凸块（36）围绕中心设置的凸块（32）基本上相等且圆形地设置。 相对于多个接地凸起和用于提供特性阻抗的空气的介电常数来确定中心设置的凸起的预定凸起直径和凸起间距。

公开(公告)号：US07109922B2

公开(公告)日：2006-09-19

申请号：US10508716

申请日：2003-04-15

Applicant: Amir Shmuel

Inventor： Amir Shmuel

IPC: H01Q1/38 ,  H04B1/38

CPC classification number: H01Q21/0025 ,  H01P5/107 ,  H01Q1/3233 ,  H01Q9/30 ,  H01Q9/40 ,  H01Q21/08 ,  H01Q25/00 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/141 ,  H05K2201/09618

Abstract: ABSTRACTA transceiver (20) for a millimeter wave signal, consisting of a PCB (140) having PCB microstrip lines (141) and PCB waveguide apertures (159), and one or more transmitter modules (22) and one or more receiver modules (24, 26, 28) mounted on the PCB. Each module has a single microstrip-waveguide transition (34, 48) and a microstrip-microstrip transition (47, 49). The microstrip-waveguide transition of each module couples to one of the PCB waveguide apertures via a PCB-module waveguide-waveguide transition (167). The microstrip-microstrip transition of each module couples to one of the PCB microstrip lines via a PCB-module microstrip-microstrip transition (165). The PCB-module transitions are low tolerance, facilitating implementation of the transceiver.

Abstract translation: 用于毫米波信号的ABSTRACTA收发器（20）由具有PCB微带线（141）和PCB波导孔（159）的PCB（140）和一个或多个发射器模块（22）和一个或多个接收器模块（24）组成 ，26,28）安装在PCB上。 每个模块具有单个微带波导过渡（34,48）和微带 - 微带过渡（47,49）。 每个模块的微带波导转换通过PCB模块波导 - 波导过渡（167）耦合到PCB波导孔之一。 每个模块的微带 - 微带转换通过PCB模块微带 - 微带过渡（165）耦合到PCB微带线之一。 PCB模块转换是低容限，便于实现收发器。

公开(公告)号：US20060189212A1

公开(公告)日：2006-08-24

申请号：US11359739

申请日：2006-02-22

Applicant: Hazelton Avery ,  Patrick Casher ,  Richard Nelson ,  Kent Regnier

Inventor： Hazelton Avery ,  Patrick Casher ,  Richard Nelson ,  Kent Regnier

IPC: H01R13/648

CPC classification number: H05K1/0219 ,  H01R12/724 ,  H01R13/6464 ,  H01R13/6587 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: Stacked receptacles in a connector that each provide side-by-side differential signal contacts, are attached to a circuit board without additional width to accommodate multiple layers of differential signals by using connector wafer inserts that rotate the side-by-side positioned differential signal contacts to front-to-back contacts.

公开(公告)号：US20060160421A1

公开(公告)日：2006-07-20

申请号：US11038708

申请日：2005-01-20

Applicant: John Dangler ,  Matthew Doyle ,  Thomas Kidd ,  Bradley Martin ,  Kevin Przybylski ,  Jason Stoll

Inventor： John Dangler ,  Matthew Doyle ,  Thomas Kidd ,  Bradley Martin ,  Kevin Przybylski ,  Jason Stoll

IPC: H01R13/648

CPC classification number: H05K1/0218 ,  H01B7/0861 ,  H05K1/0393 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0715 ,  H05K2201/09318 ,  H05K2201/09618

Abstract: In a flat flex cable, signal lines are surrounded by logic ground planes above and below which are viaed together left and right. The ground planes coupled with the flex cable dielectric determine characteristic the impedance and attenuation of the cable and provide differential signal EMI shielding. All signal layers and logic ground planes are enclosed within the two outermost shield layers which are viaed together left and right and around the connectors to enclose both signal layers and logic ground planes to provide common mode EMI shielding.

Abstract translation: 在扁平柔性电缆中，信号线被上下逻辑接地层包围，左右两侧通过。 与柔性电缆介质耦合的接地层确定电缆的阻抗和衰减特性，并提供差分信号EMI屏蔽。 所有信号层和逻辑接地层都被封闭在两个最外面的屏蔽层内，这两个最外面的屏蔽层一起左右连接并连接在一起，以封闭信号层和逻辑接地层以提供共模EMI屏蔽。