公开(公告)号：US20180269160A1

公开(公告)日：2018-09-20

申请号：US15461465

申请日：2017-03-16

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ting-Feng Su ,  Chia-Jen Chou

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/3737 ,  H01L23/5383 ,  H01L23/5386

Abstract: A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

公开(公告)号：US10079222B2

公开(公告)日：2018-09-18

申请号：US15353721

申请日：2016-11-16

Applicant: Powertech Technology Inc.

Inventor： Chien-Wei Chou ,  Yong-Cheng Chuang

IPC: H01L23/48 ,  H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L25/0657 ,  H01L21/4821 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2924/014

Abstract: A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.

公开(公告)号：US10002848B1

公开(公告)日：2018-06-19

申请号：US15619988

申请日：2017-06-12

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang-Chien ,  Nan-Chun Lin

IPC: H01L21/48 ,  H01L25/065 ,  H01L21/027 ,  H01L23/485 ,  G03F7/004

CPC classification number: H01L25/0652 ,  G03F7/0041 ,  H01L21/0273 ,  H01L21/4857 ,  H01L22/14 ,  H01L22/20 ,  H01L23/485 ,  H01L23/49822

Abstract: A conductive layer is formed on the first zone of a carrier. The redistribution layer is formed on the conductive layer on the first zone and the second zone of the carrier. Then an open-test and a short-test are performed to the redistribution layer. Since the conductive layer and the parts of the redistribution layer formed on the conductive layer constitute a closed loop, a load is presented if the redistribution layer is formed correctly. In addition, no load is presented if the redistribution layer is formed correctly since the parts of the redistribution layer formed on the second zone of the carrier constitute an open loop. Therefore, whether the redistribution layer is flawed or not is determined before the dies are boned on the redistribution layer. Thus, no waste of the good die is occurred because of the flawed redistribution layer.

公开(公告)号：US09998350B2

公开(公告)日：2018-06-12

申请号：US15298246

申请日：2016-10-20

Applicant: Powertech Technology Inc.

Inventor： Chih-Hui Yeh ,  Chih-Wei Lee

IPC: H04L12/26 ,  H04B7/04 ,  H04B7/0413

CPC classification number: H04L43/50 ,  H04B7/0413

Abstract: A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal, wherein the first testing signal and the second testing signal are outputted by the tester, and through the transfer interface, the double frequency testing signal is shared and transmitted to the socket group for testing at least two memory packages disposed on the socket group.

公开(公告)号：US20180114786A1

公开(公告)日：2018-04-26

申请号：US15423597

申请日：2017-02-03

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Chi-An Wang

IPC: H01L25/00 ,  H01L21/48 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

公开(公告)号：US20180114734A1

公开(公告)日：2018-04-26

申请号：US15782857

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/488 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

公开(公告)号：US09899307B2

公开(公告)日：2018-02-20

申请号：US15245605

申请日：2016-08-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Kuo-Ting Lin ,  Chia-Wei Chang

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/1058 ,  H01L2924/1816 ,  H01L2924/18162

Abstract: A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.

公开(公告)号：US09837384B2

公开(公告)日：2017-12-05

申请号：US15245653

申请日：2016-08-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chia-Wei Chang ,  Kuo-Ting Lin

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78 ,  H01L23/04 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0239 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06179 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out multi-chip package has a first redistribution layer and a plurality of chips encapsulated in an encapsulant. A dielectric layer and a second redistribution layer are formed on the encapsulant. A bottom surface of the encapsulant is formed when forming the encapsulant. The first redistribution layer has a plurality of connecting surfaces exposed on the bottom surface of the encapsulant. The dielectric layer is formed on the bottom surface of the encapsulant without covering the connecting surfaces. The second redistribution layer includes a plurality of bump pads coupled to the connecting surfaces. The fan-out circuitry is covered by the dielectric layer. Thereby, a multi-chip package is able to reduce possible damages to the active surfaces and bonding pads of the chips during packaging process.

公开(公告)号：US09831219B2

公开(公告)日：2017-11-28

申请号：US15491982

申请日：2017-04-20

Applicant: Powertech Technology Inc.

Inventor： Yong-Cheng Chuang ,  Kuo-Ting Lin ,  Li-Chih Fang ,  Chia-Jen Chou

IPC: H01L21/56 ,  H01L25/18 ,  H01L21/78 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

公开(公告)号：US20170317041A1

公开(公告)日：2017-11-02

申请号：US15263391

申请日：2016-09-13

Applicant: Powertech Technology Inc.

Inventor： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L24/06 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stackable semiconductor package and manufacturing method thereof are provided. The stackable semiconductor package includes carrier, first RDL, encapsulation layer, vertical interposers, second RDL, and chip. The carrier has first surface in which the first RDL and the encapsulation layer are formed thereon. The first RDL includes first pads and second pads. The encapsulation layer covers the first RDL and has outer surface. The vertical interposers are disposed in the encapsulation layer to electrically connect with the first RDL. The second RDL is formed on the outer surface to electrically connect with the vertical interposers. The carrier includes terminal holes and chip-accommodating hole. The terminal holes correspondingly expose the second pads. The chip-accommodating hole exposes the first pads. The chip is mounted on the encapsulation layer through the chip-accommodating hole to electrically connect with the first pads.