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    Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross point arrays
    101.
    发明授权
    Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross point arrays 有权
    用于补偿数据信号以影响交叉点阵列中影响存储器单元的参数变化的电路和技术

    公开(公告)号：US08705260B2

    公开(公告)日：2014-04-22

    申请号：US13728676

    申请日：2012-12-27

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

    IPC: G11C5/02 ,  G11C11/21

    CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.

    Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为补偿影响存储器元件的操作的参数变化，诸如基于第三维存储器的存储器元件 技术。 在至少一些实施例中，集成电路包括交叉点阵列，其包括布置在字线和位线之间的存储器元件，其中参数可影响存储器元件的操作特性。 集成电路还包括数据信号调整器，其被配置为基于该参数来修改操作特性以补偿与操作特性的目标值的偏差。 在一些实施例中，诸如电阻性存储器元件的存储器元件被配置为产生具有与参数变化无关的基本上处于目标值的幅度的数据信号。

    FIELD PROGRAMMABLE GATE ARRAYS USING RESISTIVITY-SENSITIVE MEMORIES
    103.
    发明申请
    FIELD PROGRAMMABLE GATE ARRAYS USING RESISTIVITY-SENSITIVE MEMORIES 审中-公开
    现场可编程门阵列使用电阻敏感记忆

    公开(公告)号：US20130222010A1

    公开(公告)日：2013-08-29

    申请号：US13724789

    申请日：2012-12-21

    Applicant: Unity Semiconductor Corporation

    Inventor： Robert Norman

    IPC: H03K19/177

    CPC classification number: H03K19/177 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

    Abstract: Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

    Abstract translation: 描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件， 敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。 存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。 两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件 跨越终端。 存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

    ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY
    104.
    发明申请
    ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY 有权

    公开(公告)号：US20130135920A1

    公开(公告)日：2013-05-30

    申请号：US13658697

    申请日：2012-10-23

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Chang Hua Siau

    IPC: G11C11/21

    CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

    REWRITABLE MEMORY WITH NON-LINEAR MEMORY ELEMENT
    105.
    发明申请
    REWRITABLE MEMORY WITH NON-LINEAR MEMORY ELEMENT 失效
    具有非线性记忆元素的可恢复存储器

    公开(公告)号：US20040170040A1

    公开(公告)日：2004-09-02

    申请号：US10604556

    申请日：2003-07-30

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

    IPC: G11C019/08

    CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77

    Abstract: A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

    Abstract translation: 公开了一种使用具有非线性IV特性的电阻性存储单元元件的可重写存储器。 在某些存储器阵列中非线性是重要的，以防止未选择的单元被干扰并减少所需的电流。 非线性是指元件将大多数电流阻塞到一定水平的能力，但是一旦达到该电平，该元件允许超过该电平的大部分电流流动。

    2-Terminal trapped charge memory device with voltage switchable multi-level resistance
    106.
    发明申请
    2-Terminal trapped charge memory device with voltage switchable multi-level resistance 失效
    2端子捕获充电存储器件，具有可切换多电平电阻

    公开(公告)号：US20040160812A1

    公开(公告)日：2004-08-19

    申请号：US10634636

    申请日：2003-08-04

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Christophe J. Chevallier

    IPC: G11C011/00

    CPC classification number: G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/165

    Abstract: A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or insulating materials of single-crystalline, poly-crystalline or amorphous structure while containing current carrier traps whose respective energy levels and degrees of carrier occupancy, modifiable by the height and width of an applied write voltage pulse, determine the resistance. The mechanism of modification can be through carrier tunneling, free carrier capturing, trap-hopping conduction or Frenkel-Poole conduction. The current carrier traps can be created with dopant varieties or an initialization procedure.

    Abstract translation: 公开了具有可电压切换的多电平电阻的2端子俘获电荷存储器件。 捕获的电荷存储器件具有夹在两个电极之间的俘获电荷存储器体。 捕获的电荷存储器主体可以由单晶，多晶或非晶结构的各种半导体或绝缘材料制成，同时包含其各自的能级和载体占有率的载流子阱，其可由 施加写电压脉冲，确定电阻。 修饰的机制可以通过载体隧穿，自由载体捕获，陷阱跳跃传导或Frenkel-Poole传导。 可以用掺杂剂品种或初始化程序产生当前载体陷阱。

    Method and a device for detecting crystalline defects in a substrate by dark field and photoluminescence
    109.
    发明授权
    Method and a device for detecting crystalline defects in a substrate by dark field and photoluminescence 有权

    公开(公告)号：US12196681B1

    公开(公告)日：2025-01-14

    申请号：US18770918

    申请日：2024-07-12

    Applicant: UNITY SEMICONDUCTOR

    Inventor： Hadrien Vergnet

    IPC: G01N21/64 ,  G01N21/95

    Abstract: A device for detecting monocrystalline substrate defects, wherein a normal to the surface of the substrate is tilted by a tilt angle being contained in an angle plane, perpendicular to the surface, the device includes a detector, an illumination light source having a light beam, and arranged in a first position and/or a second position, an excitation light source illuminating the substrate and producing an emission of photoluminescence light by the substrate, imaging means imaging the substrate according to a detector field of view producing at least one image of the substrate, and processing means detecting crystalline defects using the substrate image, each illumination light source and the imaging means are arranged in a dark-field configuration, and in the first position, the illuminating light beam is parallel or quasi-parallel to the angle plane, and in the second position, the illuminating light beam is parallel or quasi-parallel to a perpendicular plane.

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