公开(公告)号：US09666708B2

公开(公告)日：2017-05-30

申请号：US15120705

申请日：2014-03-26

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Robert S. Chau ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/02 ,  H01L21/033 ,  H01L29/08 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0332 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

公开(公告)号：US20170104094A1

公开(公告)日：2017-04-13

申请号：US15389255

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/40 ,  H01L21/02 ,  H01L29/36 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/268 ,  H01L29/20 ,  H01L21/306

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US09590069B2

公开(公告)日：2017-03-07

申请号：US14752365

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/66 ,  H01L21/338 ,  H01L29/205 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/223 ,  H01L29/778 ,  H01L29/08 ,  H01L29/423 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US20160315153A1

公开(公告)日：2016-10-27

申请号：US15197615

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/20 ,  H01L27/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L23/66 ,  H01L29/04 ,  H01L29/205

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20160079359A1

公开(公告)日：2016-03-17

申请号：US14946718

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/324 ,  H01L21/225 ,  H01L21/3213 ,  H01L21/31 ,  H01L21/311 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20160035860A1

公开(公告)日：2016-02-04

申请号：US14831307

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/66

CPC classification number: H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nano-wire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract translation: 本公开的实施例提供了用于减小纳米线晶体管中的寄生电阻的接触技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的隔离层，包括形成在隔离层上的纳米线材以提供晶体管的沟道的沟道层以及与沟道层耦合的接触， 所述触点被配置为在至少一个平面尺寸中围绕所述沟道层的纳米线材料并且为所述晶体管提供源极端子或漏极端子。

公开(公告)号：US20150072498A1

公开(公告)日：2015-03-12

申请号：US14543841

申请日：2014-11-17

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Robert S. Chau ,  Marko Radosavljevic ,  Han Wui Then ,  Scott B. Clendenning ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/223 ,  H01L21/228 ,  H01L21/28

CPC classification number: H01L29/66803 ,  B82Y10/00 ,  H01L21/2233 ,  H01L21/228 ,  H01L21/28264 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract translation: 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。

公开(公告)号：US12148747B2

公开(公告)日：2024-11-19

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Pratik Koirala ,  Nicole K. Thomas ,  Paul B. Fischer ,  Adel A. Elsherbini ,  Tushar Talukdar ,  Johanna M. Swan ,  Wilfred Gomes ,  Robert S. Chau ,  Beomseok Choi

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US12107060B2

公开(公告)日：2024-10-01

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US20240204091A1

公开(公告)日：2024-06-20

申请号：US18084438

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Heli Vora ,  Marko Radosavljevic ,  Pratik Koirala ,  Han Wui Then ,  Michael Beumer ,  Ahmad Zubair ,  Samuel Bader

IPC: H01L29/778 ,  H01L21/285 ,  H01L21/306 ,  H01L29/20 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66462

Abstract: Devices, transistor structures, systems, and techniques are described herein related to low aluminum concentration aluminum gallium nitride interlayers for group III-nitride enhancement mode transistors. The low aluminum concentration aluminum gallium nitride interlayer includes a lower aluminum concentration than a polarization layer of the transistor, such that the polarization layer induces a two-dimensional electron gas in a semiconductor layer of the transistor. The low aluminum concentration aluminum gallium nitride interlayer may be implemented as an etch stop layer, as a gate liner, or both.