公开(公告)号：US08994170B2

公开(公告)日：2015-03-31

申请号：US13778687

申请日：2013-02-27

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/00

CPC classification number: H01L24/49 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/02375 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/0901 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip package. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate.

Abstract translation: 半导体单元包括在其前表面具有左列和右列触点的芯片。 互连焊盘被提供在芯片的前表面上并且连接到至少一些触点，例如通过迹线或包括引线键合的布置。 单独的互连焊盘或互连焊盘和一些触点提供外部连接元件的阵列。 该阵列包括一些外部连接元件的反转对，其中连接到或结合右触点的外部连接元件设置在并入或连接到左触点的外部连接元件的左侧。 这种单元可以用于多芯片封装。 反向连接简化了路由，特别是在两个芯片的相应触点连接到封装基板上的公共端子的情况下。

公开(公告)号：US08981547B2

公开(公告)日：2015-03-17

申请号：US14244060

申请日：2014-04-03

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L21/02 ,  G06F1/18

CPC classification number: G06F1/16 ,  G06F1/18 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06156 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic assembly 5 can include first and second microelectronic packages 10a, 10b mounted to respective first and second opposed surfaces 61, 62 of a circuit panel 60. Each microelectronic package 10a, 10b can include a substrate 20 having first and second apertures 26a, 26b extending between first and second surfaces 21, 22 thereof, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface of the substrate and a plurality of contacts 35 exposed at the surface of the respective microelectronic element and aligned with at least one of the apertures, and a plurality of terminals 25a exposed at the second surface in a central region 23 thereof. The apertures 26a, 26b of each substrate 20 can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 of each substrate 20 can be disposed between the first and second axes 29a, 29b of the respective substrate 20.

Abstract translation: 微电子组件5可以包括安装到电路板60的相应的第一和第二相对表面61,62的第一和第二微电子封装10a，10b。每个微电子封装10a，10b可以包括具有第一和第二孔26a，26b的衬底20 在其第一表面21和第二表面22之间延伸，第一和第二微电子元件30a，30b各自具有面向基板的第一表面的表面31和暴露在相应微电子元件的表面处并与之对准的多个触点35 至少一个孔，以及在其中心区域23处在第二表面处暴露的多个端子25a。 每个基板20的孔26a，26b可以具有在相应孔的长度方向上延伸的第一和第二平行轴线29a，29b。 每个基板20的第二表面22的中心区域23可以设置在各个基板20的第一和第二轴线29a，29b之间。

公开(公告)号：US20140367866A1

公开(公告)日：2014-12-18

申请号：US14472991

申请日：2014-08-29

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni ,  Richard Dewitt Crisp ,  Ilyas Mohammed

IPC: H01L23/00 ,  H01L27/108 ,  H01L23/12

CPC classification number: H01L23/481 ,  G11C5/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/061 ,  H01L2224/091 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/301 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Abstract translation: 微电子封装可以包括具有第一和第二相对表面的衬底，至少两对微电子元件和在第二表面处暴露的多个端子。 每对微电子元件可以包括上微电子元件和下微电子元件。 这些微电子元件对可以在平行于衬底的第一表面的水平方向上彼此完全间隔开。 每个下部微电子元件可以具有面向基板的第一表面的前表面和在前表面处的多个触点。 每个上部微电子元件的表面可以至少部分地覆盖在其对中的下部微电子元件的后表面。 微电子封装还可以包括从每个下部微电子元件的至少一些触点延伸到至少一些端子的电连接。

公开(公告)号：US20140239491A1

公开(公告)日：2014-08-28

申请号：US13778687

申请日：2013-02-27

Applicant: INVENSAS CORPORATION

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/00

CPC classification number: H01L24/49 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/02375 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/0901 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate.

Abstract translation: 半导体单元包括在其前表面具有左列和右列触点的芯片。 互连焊盘被提供在芯片的前表面上并且连接到至少一些触点，例如通过迹线或包括引线键合的布置。 单独的互连焊盘或互连焊盘和一些触点提供外部连接元件的阵列。 该阵列包括一些外部连接元件的反转对，其中连接到或结合右触点的外部连接元件设置在并入或连接到左触点的外部连接元件的左侧。 这样的单元可以用在多芯片中。 反向连接简化了路由，特别是在两个芯片的相应触点连接到封装基板上的公共端子的情况下。

公开(公告)号：US20140217617A1

公开(公告)日：2014-08-07

申请号：US13758412

申请日：2013-02-04

Applicant: INVENSAS CORPORATION

Inventor： Belgacem Haba ,  Wael Zohni

IPC: H01L25/07

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3736 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/07 ,  H01L2224/04042 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/50 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.

Abstract translation: 微电子封装可以包括具有在第一和第二横向方向上延伸的第一和第二相对表面的基板和在第一和第二表面之间延伸的开口，并且限定第一和第二不同部分，每个沿着沿着第一方向延伸的共同轴线延伸， 以及第二微电子元件，每个具有面向衬底的第一表面的前表面和在相应的前表面处的接触柱，在第二表面处暴露的多个端子以及与相应的第一和第二表面对准的第一和第二电连接 开口的部分并且从相应的第一和第二微电子元件的至少一些触点延伸到至少一些端子。 第一和第二微电子元件的接触柱可以与开口的相应的第一和第二部分对准。

公开(公告)号：US20140110832A1

公开(公告)日：2014-04-24

申请号：US13841052

申请日：2013-03-15

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC: H01L25/065 ,  H05K1/11

CPC classification number: H01L25/0652 ,  G11C5/063 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/10159 ,  H01L2924/00

Abstract: A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.

Abstract translation: 电路板可以包括暴露在其主表面的连接位置并被配置为耦合到微电子封装的端子的触点。 连接部位可以在被配置为耦合到单个微电子封装的一组触点周围的主表面上限定外围边界。 该组联系人可以包括第一，第二，第三和第四组第一联系人。 第一和第三组第一触点的信号分配可以相对于主表面垂直的理论平面对称，具有相应的第二和第四组第一触点的信号分配。 可以将每组第一个触点设置为携带相同的信号。 可以将每组第一触点组配置为承载足以指定微电子封装的存储器存储阵列内的位置的地址信息。

公开(公告)号：US20130083584A1

公开(公告)日：2013-04-04

申请号：US13644012

申请日：2012-10-03

Applicant: INVENSAS CORPORATION

Inventor： Richard Dewitt Crisp ,  Wael Zohni

IPC: G11C5/06

CPC classification number: H01L25/105 ,  G11C5/04 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06156 ,  H01L2224/06164 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10545 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.

公开(公告)号：US10354976B2

公开(公告)日：2019-07-16

申请号：US15393068

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L21/48 ,  H01L25/065 ,  H01L21/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528 ,  H01L25/07 ,  H01L25/11 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18

Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

公开(公告)号：US10283445B2

公开(公告)日：2019-05-07

申请号：US15334606

申请日：2016-10-26

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Wael Zohni ,  Liang Wang ,  Akash Agrawal

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

公开(公告)号：US10211160B2

公开(公告)日：2019-02-19

申请号：US15257152

申请日：2016-09-06

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni ,  Cyprian Emeka Uzoh

IPC: H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31

Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.