公开(公告)号：US20120106032A1

公开(公告)日：2012-05-03

申请号：US13345227

申请日：2012-01-06

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

IPC: H01G9/025 ,  H01G9/04 ,  H01G9/15 ,  H01G7/00

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US20120094442A1

公开(公告)日：2012-04-19

申请号：US13337164

申请日：2011-12-26

Applicant: Charles W.C. Lin ,  Chia-Chung Wang

Inventor： Charles W.C. Lin ,  Chia-Chung Wang

IPC: H01L21/60

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting a first adhesive on the ledge including inserting the bump into an opening in the first adhesive, mounting a conductive layer on the first adhesive including aligning the bump with an aperture in the conductive layer, then flowing the first adhesive between the bump and the conductive layer, solidifying the first adhesive, then providing a heat spreader that includes the bump, a base and the ledge, then mounting a second adhesive on the ledge, mounting a conductive trace that includes a pad and a terminal on the second adhesive, then mounting a semiconductor device on the bump in a cavity in the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 制造半导体芯片组件的方法包括提供凸块和凸缘，将第一粘合剂安装在凸缘上，包括将凸块插入第一粘合剂中的开口中，将导电层安装在第一粘合剂上，包括使凸块与孔 在导电层中，然后使第一粘合剂在凸起和导电层之间流动，固化第一粘合剂，然后提供包括凸块，底座和凸缘的散热器，然后将第二粘合剂安装在凸缘上， 导电迹线，其包括第二粘合剂上的焊盘和端子，然后将凸块中的半导体器件安装在凸块中的空腔中，将半导体器件电连接到导电迹线并将半导体器件热连接到散热器。

公开(公告)号：US08142905B2

公开(公告)日：2012-03-27

申请号：US12738995

申请日：2009-05-29

Applicant: Terumasa Moriyama ,  Kengo Kaminaga

Inventor： Terumasa Moriyama ,  Kengo Kaminaga

IPC: B32B15/01 ,  B32B15/04 ,  B32B15/08 ,  B32B15/20

CPC classification number: H05K3/384 ,  C23C28/00 ,  C23C28/321 ,  C23C28/345 ,  C23C28/3455 ,  C25D3/562 ,  C25D3/565 ,  C25D7/0614 ,  H05K2201/0239 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/12438 ,  Y10T428/12472 ,  Y10T428/12569 ,  Y10T428/12583 ,  Y10T428/1259 ,  Y10T428/12618 ,  Y10T428/1266 ,  Y10T428/12792 ,  Y10T428/12847 ,  Y10T428/12903 ,  Y10T428/12944 ,  Y10T428/263 ,  Y10T428/27 ,  Y10T428/273

Abstract: Provided is a copper foil for a printed circuit board comprising a layer including nickel, zinc, a compound of nickel and that of zinc (hereinafter referred to a “nickel zinc layer”) on a roughened surface of a copper foil, and a chromate film layer on the nickel zinc layer, wherein the zinc add-on weight per unit area of the nickel zinc layer is 180 μg/dm2 or more and 3500 μg/dm2 or less, and the nickel weight ratio in the nickel zinc layer {nickel add-on weight/(nickel add-on weight+zinc add-on weight)} is 0.38 or more and 0.7 or less. This surface treatment technology of a copper foil is able to effectively prevent the circuit corrosion phenomenon in cases of laminating a copper foil on a resin base material and using a sulfuric acid hydrogen peroxide etching solution to perform soft etching to the circuit.

Abstract translation: 提供一种用于印刷电路板的铜箔，其包括在铜箔的粗糙表面上包含镍，锌，镍化合物和锌的层（以下称为“镍锌层”）的层，以及铬酸盐膜 镍锌层的单位面积锌添加量为180μg/ dm 2以上且3500μg/ dm 2以下，镍锌层中的镍重量比（镍添加量） - 重量/（镍附加重量+锌附加重量）}为0.38以上且0.7以下。 铜箔的表面处理技术能够有效地防止在树脂基材上层叠铜箔并使用硫酸过氧化氢蚀刻溶液对电路进行软蚀刻的情况下的电路腐蚀现象。

公开(公告)号：US20120037414A1

公开(公告)日：2012-02-16

申请号：US13269079

申请日：2011-10-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在第一层间树脂绝缘层和高电介质层上的层状电容器部分和夹着高电介质层的第一和第二层状电极。 在第一绝缘层和电容器部分上设置第二层间树脂绝缘层，并且在电容器部分和第二绝缘层上设置金属薄膜层。 在第二绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层。 安装部分设置在最外层绝缘层上，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体。 第二通孔导体将第二层状电极电连接到第二外部端子。

公开(公告)号：US08089003B2

公开(公告)日：2012-01-03

申请号：US12057654

申请日：2008-03-28

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H05K1/02

CPC classification number: H05K1/056 ,  H05K1/0393 ,  H05K2201/0355 ,  H05K2201/0382

Abstract: A printed circuit board substrate includes an insulation matrix and a waterproof layer. The insulation matrix includes a first surface and a second surface at an opposite side thereof to the first surface. The waterproof layer is formed in the insulation matrix and is arranged between the first surface and the second surface for blocking water from passing therethrough in a thicknesswise direction of the insulation matrix.

Abstract translation: 印刷电路板基板包括绝缘基体和防水层。 绝缘矩阵包括与第一表面相对的第一表面和第二表面。 防水层形成在绝缘基体中，并且布置在第一表面和第二表面之间，用于阻挡水在绝缘基体的厚度方向上穿过其中。

公开(公告)号：US08083954B2

公开(公告)日：2011-12-27

申请号：US12131932

申请日：2008-06-03

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

IPC: H01B13/00

CPC classification number: B32B37/226 ,  B32B38/06 ,  B32B2305/342 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83132 ,  H05K1/023 ,  H05K1/185 ,  H05K1/188 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.

Abstract translation: 一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。

公开(公告)号：US20110290380A1

公开(公告)日：2011-12-01

申请号：US13127905

申请日：2009-10-20

Applicant: Hironao Okayama ,  Akira Kaneko ,  Kouji Nanbu

Inventor： Hironao Okayama ,  Akira Kaneko ,  Kouji Nanbu

IPC: C22F1/08 ,  C23F1/00 ,  C22C9/00

CPC classification number: C22F1/08 ,  B32B15/01 ,  B32B15/015 ,  C22C9/00 ,  C22C38/02 ,  C22C38/44 ,  C22C38/58 ,  C30B25/18 ,  C30B29/06 ,  C30B29/16 ,  C30B29/40 ,  C30B29/52 ,  C30B33/00 ,  H01L23/142 ,  H01L31/03921 ,  H01L33/007 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/022 ,  H05K2201/0355 ,  H05K2203/1105 ,  Y02E10/50 ,  H01L2924/00

Abstract: Disclosed is a metal laminated substrate for forming an epitaxial growth film for forming a semiconductor element having high biaxial crystal orientation on a surface of a metal substrate and a method of manufacturing the metal laminated substrate. The manufacturing method includes the steps of activating at least one surface of a metal plate T1 by sputter etching or the like; activating at least one surface of a metal foil T2 made of Cu or a Cu alloy which is cold-rolled at a rolling reduction of 90% or more; laminating the metal plate and the metal foil such that an activated surface of the metal plate and an activated surface of the metal foil face each other in an opposed manner and applying cold rolling to the metal plate and the metal foil which are laminated to each other at a rolling reduction of 10% or less, for example; and biaxially orienting crystals of the metal foil by heat treatment at a temperature of not lower than 150° C. and not higher than 1000° C.

Abstract translation: 公开了一种用于形成用于在金属基板的表面上形成具有高双轴晶体取向的半导体元件的外延生长膜的金属层压基板和制造金属层叠基板的方法。 该制造方法包括通过溅射蚀刻等激活金属板T1的至少一个表面的步骤; 激活由Cu或Cu合金制成的金属箔T2的至少一个表面，其中轧制压下率为90％以上; 层压金属板和金属箔，使得金属板的活化表面和金属箔的活化表面相反地相对地面对并对彼此层压的金属板和金属箔进行冷轧 例如在压下率为10％以下的情况下。 并且在不低于150℃且不高于1000℃的温度下通过热处理将金属箔的晶体双轴取向。

公开(公告)号：US20110289770A1

公开(公告)日：2011-12-01

申请号：US13115287

申请日：2011-05-25

Applicant: Takeshi OKADA ,  Kazuhiro Kobayashi

Inventor： Takeshi OKADA ,  Kazuhiro Kobayashi

IPC: H05K3/00 ,  H05K7/06

CPC classification number: H05K3/0097 ,  B32B37/1009 ,  B32B38/0004 ,  B32B38/145 ,  B32B38/1841 ,  B32B2309/10 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2203/0156

Abstract: An apparatus for manufacturing a temporary substrate includes a jig having a table, a holding guide for positioning constituent members of the temporary substrate, a holding unit for holding the laminated constituent members, and a heater unit for performing a temporary bonding on the laminated constituent members, and further includes a drive mechanism for moving each member constituting the jig between a standby position and an in-use position. The holding guide has a plurality of step portions formed in such a manner that peripheries of the step portions define areas corresponding to outer sizes of the respective constituent members when the holding guide is moved to the in-use position. The temporary substrate has as the constituent members, a prepreg, inner metal foils respectively stacked on both surfaces of the prepreg and each having a smaller outer size than the prepreg, and outer metal foils respectively stacked on the inner metal foils and each having a larger outer size than the prepreg.

Abstract translation: 一种临时基板的制造装置，具备：具有工作台的夹具，用于定位临时基板的构成部件的保持引导件，保持该层压部件的保持部;以及用于对叠层部件进行暂时接合的加热器部 并且还包括用于使构成夹具的每个构件在待机位置和使用位置之间移动的驱动机构。 保持引导件具有多个台阶部分，其形成为当保持引导件移动到使用位置时，阶梯部分的周边限定对应于各个构成部件的外部尺寸的区域。 临时基板具有作为构成部件的预浸料坯，分别层叠在预浸料坯的两面上并且分别具有比预浸料坯小的外径的内部金属箔和分别堆叠在内部金属箔上并且各自具有较大的外部金属箔的内部金属箔 外形比预浸料。

公开(公告)号：US20110284267A1

公开(公告)日：2011-11-24

申请号：US12782900

申请日：2010-05-19

Applicant: Chen-Chuan Chang

Inventor： Chen-Chuan Chang

IPC: H05K1/00 ,  B32B38/10

CPC classification number: B32B38/10 ,  H05K3/4623 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/0355 ,  H05K2201/09127 ,  H05K2203/107 ,  Y10T156/1052

Abstract: A circuit board having a cavity is provided. The circuit board includes a first core layer, a second core layer, and a central dielectric layer. The first core layer includes a core dielectric layer and a core circuit layer, wherein the core circuit layer is disposed on the core dielectric layer. The second core layer is disposed on the first core layer. The central dielectric layer is disposed between the first core layer and the second core layer. The cavity runs through the second core layer and the central dielectric layer and exposes a portion of the core circuit layer.

Abstract translation: 提供具有空腔的电路板。 电路板包括第一芯层，第二芯层和中心电介质层。 第一芯层包括芯介质层和芯电路层，其中芯电路层设置在芯介质层上。 第二芯层设置在第一芯层上。 中心电介质层设置在第一芯层和第二芯层之间。 空腔穿过第二芯层和中心电介质层并暴露核心电路层的一部分。

公开(公告)号：US08043697B2

公开(公告)日：2011-10-25

申请号：US11918803

申请日：2006-04-17

Applicant: Masato Murakami ,  Hiroaki Yamaguchi

Inventor： Masato Murakami ,  Hiroaki Yamaguchi

IPC: B32B15/08

CPC classification number: H05K1/0346 ,  B32B15/08 ,  B32B15/20 ,  B32B27/281 ,  B32B2457/08 ,  C08G73/1067 ,  H05K3/389 ,  H05K2201/0355 ,  H05K2203/0759 ,  Y10T428/266 ,  Y10T428/31678 ,  Y10T428/31681

Abstract: A polyimide film-laminated body is composed of a metal layer and an aromatic polyimide layer formed by casting a polyamic acid solution composition, comprising 3,3′,4,4′-biphenyltetracarboxylic dianhydride as an essential tetracarboxylic dianhydride component and with introduction of a specific diamine component, onto a metal foil. The polyimide film-laminated body has an excellent gas permeation rate and moisture permeation rate, with heat resistance, a high elastic modulus and a low linear expansion coefficient, and with reduced foaming and delamination during the high-temperature steps for formation of the laminated body.

Abstract translation: 聚酰亚胺膜层压体由金属层和通过浇铸聚酰胺酸溶液组合物形成的芳族聚酰亚胺层组成，所述聚酰胺酸溶液组合物包含3,3'，4,4'-联苯四羧酸二酐作为主要的四羧酸二酐组分，并引入 特定的二胺组分，在金属箔上。 聚酰亚胺膜层压体具有优异的气体渗透速率和水分渗透速率，具有耐热性，高弹性模量和低线膨胀系数，并且在用于形成层压体的高温步骤期间具有减少的起泡和分层 。