公开(公告)号：US11889617B1

公开(公告)日：2024-01-30

申请号：US17901208

申请日：2022-09-01

Applicant: Baidu USA LLC

Inventor： Zhenwei Yu ,  Yun Ji

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02

CPC classification number: H05K1/0237 ,  H05K1/116 ,  H05K3/42 ,  H05K2201/09627 ,  H05K2201/09672

Abstract: A printed circuit board includes first and second surfaces, first and second layers, and first and second vias. The first via extends from a first layer to the second surface and includes a first portion that is on a conductive path between the first layer and the second layer and a second portion that is not on the conductive path. A length of the first portion of the first via is greater than that of the second portion of the first via. The second via extends from the second surface to the second layer. The second via includes a first portion that is on the conductive path between the first layer and the second layer and a second portion that is not on the conductive path. A length of the first portion of the second via is greater than that of the second portion of the second via.

公开(公告)号：US20230300984A1

公开(公告)日：2023-09-21

申请号：US17939546

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjin LEE ,  Jonghoon KIM ,  Kyoungsun KIM ,  Sungjoo PARK ,  Jinseong YUN ,  Young-Ho LEE ,  Jeonghyeon CHO ,  Heejin CHO

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0298 ,  H05K3/4038 ,  H05K2201/09627

Abstract: An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

公开(公告)号：US11678434B2

公开(公告)日：2023-06-13

申请号：US17286939

申请日：2019-11-14

Applicant: Continental Automotive France ,  Continental Automotive GmbH

Inventor： Daniel Guerra ,  Philippe Lehue

IPC: H05K1/02

CPC classification number: H05K1/0268 ,  H05K2201/0776 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/09672

Abstract: A multilayer printed circuit having a control circuit including n vias that are connected in series between a first and a second electrical terminal so that an applied electric current passes at least partially through each one of the n vias. The control circuit includes track portions in each one of the layers, each one of the n vias connecting a track portion of one layer to a track portion of another layer. The control circuit includes a measurement device for measuring a potential difference across its terminals, storage for storing a threshold value and a comparator for comparing the potential difference with the threshold value so as to validate the printed circuit when the potential difference is lower than the threshold value.

公开(公告)号：US20180352652A1

公开(公告)日：2018-12-06

申请号：US15609103

申请日：2017-05-31

Applicant: International Business Machines Corporation

Inventor： MATTHEW S. DOYLE ,  JEFFREY N. JUDD ,  JOSEPH KUCZYNSKI ,  SCOTT D. STRAND ,  TIMOTHY J. TOFIL

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/40 ,  H05K3/30 ,  H02H3/08 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/0293 ,  H05K1/116 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/0326 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10151 ,  H05K2203/125

Abstract: A process of utilizing a heat-activated conductive spinel material for PCB via overcurrent protection includes forming a PCB laminate structure that includes a spinel-doped insulator layer having a heat-activated conductive spinel material incorporated into a dielectric material as a spinel-based electrically non-conductive metal oxide. A sensing via is formed in the PCB laminate structure at a location that is proximate to a power via in the PCB laminate structure. The sensing via is electrically isolated from the power via by a region of the spinel-doped insulator layer and is electrically connected to a monitoring component configured to detect current flow through the sensing via that results from an overcurrent event in the power via that generates sufficient heat to cause the spinel-based electrically conductive metal oxide to release metal nuclei into the region to provide a conductive pathway through the region from the power via to the sensing via.

公开(公告)号：US09992871B2

公开(公告)日：2018-06-05

申请号：US14937047

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mathew J Manusharow

IPC: H05K1/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0234 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/4644 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2201/0776 ,  H05K2201/09627 ,  H05K2201/10015 ,  H05K2203/14

Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.

公开(公告)号：US20170135211A1

公开(公告)日：2017-05-11

申请号：US14937047

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mathew J. Manusharow

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/32 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/116 ,  H05K1/0234 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/4644 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2201/0776 ,  H05K2201/09627 ,  H05K2201/10015 ,  H05K2203/14

Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.

公开(公告)号：US09615459B2

公开(公告)日：2017-04-04

申请号：US14416671

申请日：2014-12-31

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Jianyong Fu ,  Dongsheng Guo

IPC: H01F5/00 ,  H05K1/16

CPC classification number: H05K1/165 ,  H05K3/46 ,  H05K2201/09627 ,  H05K2201/09672

Abstract: An inductor, a circuit board and a method for forming an inductor are provided. The inductor comprises: a first pad arranged on a first metal wiring layer of a circuit board; a second pad arranged on a second metal wiring layer of the circuit board; and a first hole with conducting medium filled therein, one end of the first hole being located in the first pad and the other end thereof being located in the second pad. The inductor can effectively reduce the area of the circuit occupied by the inductor.

公开(公告)号：US09571059B2

公开(公告)日：2017-02-14

申请号：US14672138

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Jianfang Olena Zhu ,  Chung-Hao Joseph Chen ,  Ana M. Yepes

IPC: H01P5/12 ,  H03H7/38 ,  H03H7/01 ,  H05K1/02

CPC classification number: H03H7/383 ,  H03H7/0123 ,  H03H7/427 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

Abstract translation: 公开了并联通孔设计，以改善嵌入式共模扼流圈滤波器设计的阻抗匹配。 特别适用于四层印刷电路板上的这种设计，并行通孔设计有效地抑制了差分对的反射。 通过并联连接通孔，整个通孔结构的电感减小，同时电容同时增加。 通过适当选择并联通孔的数量和它们之间的间距，可以在感兴趣的频率范围内良好地控制并联通孔的阻抗。 因此，可以提高阻抗匹配，并且降低四层印刷电路板共模扼流滤波器设计的回波损耗。

公开(公告)号：US20170027057A1

公开(公告)日：2017-01-26

申请号：US15216735

申请日：2016-07-22

Applicant: IBIDEN CO., LTD.

Inventor： Masatoshi KUNIEDA ,  Takafumi OKUMURA

IPC: H05K1/11 ,  H01L23/31 ,  H05K1/09 ,  H01L23/00 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K1/115 ,  H01L23/3114 ,  H01L24/14 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H05K3/185 ,  H05K3/422 ,  H05K3/424 ,  H05K2201/09545 ,  H05K2201/09627 ,  H05K2201/09645 ,  H05K2203/0723

Abstract: A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.

Abstract translation: 一种制造印刷电路板的方法包括在绝缘层的表面上形成图案化催化剂膜，该图案化催化剂膜包括用于化学镀的催化剂，使得图案化的催化剂膜具有与导体电路相对应的图案，并且在 图案化的催化剂膜，使得导体金属沉积在图案化的催化剂膜上，并且导体电路形成在绝缘层的表面上。

公开(公告)号：US09451704B2

公开(公告)日：2016-09-20

申请号：US14062264

申请日：2013-10-24

Applicant: Nitto Denko Corporation

Inventor： Terukazu Ihara ,  Jun Ishii ,  Naohiro Terada

IPC: H05K1/00 ,  H05K3/10 ,  G11B5/48 ,  H05K3/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/05 ,  H05K3/06

CPC classification number: H05K3/10 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/4685 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: A plurality of suspension boards and an inspection substrate are integrally supported by a support frame. In each suspension board, a line is formed on a conductive first support substrate via a first insulating layer. The first support substrate and the line are electrically connected by a first via in the first insulating layer. In the inspection substrate, a conductor layer is formed on a conductive second support substrate with a second insulating layer sandwiched therebetween. The second support substrate and the conductor layer are electrically connected by a second via in the second insulating layer. The first via and the second via have the same configuration.

Abstract translation: 多个悬挂板和检查基板由支撑框架一体地支撑。 在每个悬挂板中，经由第一绝缘层在导电的第一支撑基板上形成线。 第一支撑基板和线通过第一绝缘层中的第一通孔电连接。 在检查基板中，导电层形成在导电性的第二支撑基板上，其间夹着第二绝缘层。 第二支撑基板和导体层通过第二绝缘层中的第二通孔电连接。 第一通孔和第二通孔具有相同的配置。