公开(公告)号：US07274100B2

公开(公告)日：2007-09-25

申请号：US10875473

申请日：2004-06-23

Applicant: Mark Pavier ,  Tim Sammon

Inventor： Mark Pavier ,  Tim Sammon

IPC: H01L23/34

CPC classification number: H01L23/5383 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/095 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/09672 ,  Y10S257/924 ,  H01L2224/0401

Abstract: An integrated circuit which includes a circuit board having passive elements embedded in its body.

Abstract translation: 一种集成电路，其包括具有嵌入其主体中的无源元件的电路板。

公开(公告)号：US20070205780A1

公开(公告)日：2007-09-06

申请号：US11308094

申请日：2006-03-06

Applicant: Benjamin Eldridge

Inventor： Benjamin Eldridge

IPC: G01R31/02

CPC classification number: G01R1/07378 ,  G01R31/2889 ,  H05K1/0216 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09672

Abstract: Systems and methods for providing a stack with a guard plane embedded in the stack are disclosed. An electrical apparatus can be made by forming a stack comprising an electrically conductive signal structure, an electrical guard structure, and an electrically insulating structure disposed between the signal structure and the guard structure. The signal structure, insulating structure, and guard structure can be aligned one with another in the stack.

Abstract translation: 公开了一种用于提供具有嵌入堆叠中的保护平面的堆叠的系统和方法。 可以通过形成包括导电信号结构，电保护结构和布置在信号结构和保护结构之间的电绝缘结构的堆叠来制造电气设备。 信号结构，绝缘结构和防护结构可以在堆叠中彼此对准。

公开(公告)号：US20070184724A1

公开(公告)日：2007-08-09

申请号：US11734263

申请日：2007-04-11

Applicant: Luc Adriaenssens ,  Amid Hashim ,  Troy Long

Inventor： Luc Adriaenssens ,  Amid Hashim ,  Troy Long

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes PCB substrates made of materials having different dielectric frequency characteristics.

Abstract translation: 提供连接器，用于当使用低串扰插头时同时提高NEXT高频性能，并且当使用高串扰插头时NEXT低频性能。 连接器包括由具有不同介电频率特性的材料制成的PCB衬底。

公开(公告)号：US20070113966A1

公开(公告)日：2007-05-24

申请号：US11532715

申请日：2006-09-18

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: B32B37/00 ,  G08B13/14

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A process for forming a portion of a package or envelope bearing printed indicia, a label bearing printed indicia or a sheet bearing printed indicia includes providing a substrate which constitutes a portion of the package, label or sheet to a printing apparatus, and utilizing the printing apparatus or an adjunct to the printing apparatus to form at least one electrically conductive component of an EAS and/or RFID tag on the substrate substantially contemporaneously with the printing of the indicia on the substrate. The forming of the electrically conductive component on the substrate is accomplished slightly prior to the printing of the indicia on the substrate, slightly after the printing of the indicia on the substrate and at the same time as the printing of the indicia on the substrate.

Abstract translation: 用于形成承载印刷标记的包装或信封的一部分的方法，带有印刷标签的印刷标签或承载印刷标记的片材的方法包括将构成包装，标签或片材的一部分的基材提供到印刷装置，并且利用印刷 装置或辅助装置，以基本上同时在基板上印刷标记而在基板上形成EAS和/或RFID标签的至少一个导电部件。 导电组件在衬底上的形成在印刷衬底上的标记之前略微地完成，稍后在衬底上印刷标记之后，并且与衬底上的标记的印刷同时进行。

公开(公告)号：US20070090912A1

公开(公告)日：2007-04-26

申请号：US11444110

申请日：2006-05-30

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H01F5/00

CPC classification number: H01F17/0013 ,  H01F17/0033 ,  H01F2017/002 ,  H01L23/645 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0298 ,  H05K1/165 ,  H05K2201/09672 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embedded inductor suitable for a wiring board is provided. The wiring board having a plurality of patterned conductive layers and a plurality of insulating layers, and one of the insulating layers is disposed between any two adjacent of the patterned conductive layers. The embedded inductor at least includes a first conductive trace, a second conductive trace, a third conductive trace, a first conductive structure, and a second conductive structure. These conductive traces are respectively formed of different patterned conductive layers of the wiring board. The first conductive structure and the second conductive structure passing through the insulating layers connect the conductive traces in a spiral pattern. The embedded inductor with such spiral pattern is arranged on a plane that is perpendicular to the patterned conductive layers of the wiring board.

Abstract translation: 提供了适用于接线板的嵌入式电感器。 具有多个图案化导电层和多个绝缘层的布线板，并且其中一个绝缘层设置在图案化导电层的任意两个相邻之间。 嵌入式电感器至少包括第一导电迹线，第二导电迹线，第三导电迹线，第一导电结构和第二导电结构。 这些导电迹线分别由布线板的不同图案化导电层形成。 通过绝缘层的第一导电结构和第二导电结构以螺旋图案连接导电迹线。 具有这种螺旋图案的嵌入式电感器被布置在垂直于布线板的图案化导电层的平面上。

公开(公告)号：US20070090398A1

公开(公告)日：2007-04-26

申请号：US11583212

申请日：2006-10-18

Applicant: William McKinzie

Inventor： William McKinzie

IPC: H01L31/00

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US07209361B2

公开(公告)日：2007-04-24

申请号：US10914458

申请日：2004-08-09

Applicant: Reinhold Berberich ,  Dieter Busch ,  Reinfried Grimmel

Inventor： Reinhold Berberich ,  Dieter Busch ,  Reinfried Grimmel

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/162 ,  H05K1/0218 ,  H05K1/189 ,  H05K3/4691 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/09672

Abstract: An electronic device includes a first module, which is protected against electromagnetic interference, and a second module. At least the first module has multilayer printed circuit boards with at least one inner layer with conductor tracks. The at least one inner layer forms flexible connections between the printed circuit boards of the first and second modules. The at least one inner layer forms a bushing capacitor together with other conductor tracks of the first module.

Abstract translation: 一种电子设备包括被防止电磁干扰的第一模块和第二模块。 至少第一模块具有具有至少一个具有导体轨迹的内层的多层印刷电路板。 至少一个内层在第一和第二模块的印刷电路板之间形成柔性连接。 所述至少一个内层与第一模块的其它导体轨道一起形成衬套电容器。

公开(公告)号：US07202548B2

公开(公告)日：2007-04-10

申请号：US11224224

申请日：2005-09-13

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H01L29/00

CPC classification number: H01L23/5223 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: An embedded capacitors with interdigitated structure for a package carrier or a printed circuit board comprises a plurality of stacked conductive layers, at least one first via connecting structure and at least one second via connecting structure. In order to enhance the capacitance and the layout efficiency, this case fully utilizes the spaces between the via connecting structures for disposing at least one extending line extended from the via connecting structure to simultaneously increase side-to-side and layer-to-layer capacitances. Thus, the present invention provides a capacitance larger than that of conventional design.

Abstract translation: 具有用于封装载体或印刷电路板的叉指结构的嵌入式电容器包括多个层叠导电层，至少一个第一通孔连接结构和至少一个第二通孔连接结构。 为了提高电容和布局效率，这种情况充分利用通孔连接结构之间的空间，用于布置从通孔连接结构延伸的至少一条延伸线，以同时增加侧到侧和层间电容 。 因此，本发明提供比常规设计更大的电容。

公开(公告)号：US20070008059A1

公开(公告)日：2007-01-11

申请号：US11176801

申请日：2005-07-06

Applicant: Haitao Li

Inventor： Haitao Li

IPC: H01F27/28

CPC classification number: H05K1/165 ,  H05K3/0047 ,  H05K3/4638 ,  H05K2201/0352 ,  H05K2201/09672 ,  H05K2201/09727

Abstract: Selected dimensions of conductive strips on one or more layers of a multilayer substrate are increased to compensate misregistration effects associated with device fabrication. The increased dimension can be based on one or more factors such as, for example, a likely misregistration distance. In one embodiment, conductive strips from two different conductor layers follow a common path and are electrically connected by a via to provide an overlay inductor. The conductive strip in one conductor layer is made slightly wider that the conductive strip of the other conductor layer to reduce the effects of misregistration on electrical characteristics.

Abstract translation: 多层基板的一个或多个层上的导电条的选定尺寸被增加以补偿与器件制造相关的不对准效应。 增加的尺寸可以基于一个或多个因素，例如可能的不对准距离。 在一个实施例中，来自两个不同导体层的导电条跟随公共路径，并且通过通孔电连接以提供覆盖电感器。 一个导体层中的导电条被制成略宽于另一个导体层的导电条，以减少不对准对电特性的影响。

公开(公告)号：US20060290463A1

公开(公告)日：2006-12-28

申请号：US11135762

申请日：2005-05-23

Applicant: Devin Bingham ,  Daniel Ayres ,  Alvin Chow

Inventor： Devin Bingham ,  Daniel Ayres ,  Alvin Chow

IPC: H01C10/00

CPC classification number: H05K1/162 ,  H05K1/0293 ,  H05K1/0298 ,  H05K3/027 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175

Abstract: A circuit element has a substrate layer with first and second faces. A conductive first layer overlays the first surface, and a conductive second layer overlays the second surface. The first layer defines a pattern with a trimmable portion. The second layer defines a pattern having a first conductive element registered with at least a portion of the trimmable portion, and a second conductive element electrically isolated from first element and encompassing the first element. The second element may be a ground plane that has an aperture surrounding the first component, which serves as a shield to prevent damage to any elements beyond the second layer.

Abstract translation: 电路元件具有带有第一和第二面的衬底层。 导电第一层覆盖第一表面，并且导电的第二层覆盖第二表面。 第一层定义具有可调节部分的图案。 第二层限定了具有与可调节部分的至少一部分配准的第一导电元件的图案，以及与第一元件电隔离并且包围第一元件的第二导电元件。 第二元件可以是具有围绕第一部件的孔的接地平面，其用作屏蔽件以防止损坏超出第二层的任何元件。