公开(公告)号：US20070035689A1

公开(公告)日：2007-02-15

申请号：US11439912

申请日：2006-05-24

Applicant: Han-jin Ryu

Inventor： Han-jin Ryu

IPC: G02F1/1345 ,  G02F1/1333

CPC classification number: G02F1/13452 ,  H05K1/0256 ,  H05K3/28 ,  H05K2201/09909 ,  H05K2203/0588

Abstract: A printed circuit board (PCB) and a liquid crystal display (LCD) including the same are provided. The PCB includes a metal pattern formed on an insulating substrate, an insulating layer covering the metal pattern, and at least one insulating layer protecting pattern formed on the insulating layer. The LCD includes a liquid crystal panel, a backlight assembly providing light to the liquid crystal panel, a bottom chassis having at least one support protruding from a surface thereof and receiving the liquid crystal panel and the backlight assembly, and a printed circuit board (PCB) including a metal pattern formed on an insulating substrate, an insulating layer covering the metal pattern, and at least one insulating layer protecting pattern formed on the insulating layer, wherein the printed circuit board is connected to the surface of the bottom chassis.

Abstract translation: 提供了一种印刷电路板（PCB）和包括其的液晶显示器（LCD）。 PCB包括形成在绝缘基板上的金属图案，覆盖金属图案的绝缘层，以及形成在绝缘层上的至少一个绝缘层保护图案。 LCD包括液晶面板，向液晶面板提供光的背光组件，具有从其表面突出并接收液晶面板和背光组件的至少一个支撑件的底架，以及印刷电路板（PCB ），包括形成在绝缘基板上的金属图案，覆盖金属图案的绝缘层和形成在绝缘层上的至少一个绝缘层保护图案，其中印刷电路板连接到底部底盘的表面。

公开(公告)号：US20060177965A1

公开(公告)日：2006-08-10

申请号：US10539987

申请日：2004-01-14

Applicant: Ayumi Senda

Inventor： Ayumi Senda

IPC: H01L21/48 ,  H01L21/50

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/10165 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H05K3/303 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2203/167 ,  Y02P70/613

Abstract: When a semiconductor chip is mounted on a mount substrate by bonding bumps, bonding failure is caused by misalignment between the bumps. Before a semiconductor chip having a plurality of bumps is mounted on a mount substrate (3) having a plurality of bumps (4) by flip chip bonding, a resist layer (5) having a thickness larger than that of the bumps (4) is formed on the mount substrate (3) with the bumps. By patterning the resist layer (5), projecting guides (5A) of semicircular cross section are formed on the mount substrate (3) so as to protrude near the bumps (4) and from a surface on which the bumps (4) are provided, and to have guide faces (curved faces) pointing toward the bumps (4).

Abstract translation: 当通过接合凸块将半导体芯片安装在安装基板上时，由于凸块之间的不对准引起接合失败。 在通过倒装焊接将具有多个凸块的半导体芯片安装在具有多个凸块（4）的安装基板（3）上之后，具有比凸块（4）厚度大的抗蚀剂层（5） 形成在安装基板（3）上。 通过对抗蚀剂层（5）进行图案化，在安装基板（3）上形成半圆形横截面的突出导向件（5A），以便在凸起（4）附近突出并且从凸块（4）的表面 并且具有指向凸块（4）的引导面（曲面）。

公开(公告)号：US07075017B2

公开(公告)日：2006-07-11

申请号：US11014393

申请日：2004-12-16

Applicant: Kensuke Nishi ,  Yasuto Ishimaru

Inventor： Kensuke Nishi ,  Yasuto Ishimaru

IPC: H05K1/11

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/323 ,  H05K3/3452 ,  H05K2201/09709 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00

Abstract: At least a particular part of a strip conductor 2 of a wiring circuit board for mounting, wherein the strip conductor is exposed to form a stripe pattern, so that individual conductor can be connected to electrode E of an electronic component, is covered with a solder resist 3. The particular part is one section in the longitudinal direction of a strip conductor having a long end, which section includes an area overlapping an electrode which is connected to a short end and transferred in parallel in the strip width direction up to the position on the strip conductor having a long end. As a result, a structure capable of suppressing a short circuit between an electrode and a wiring pattern can be afforded to a wiring circuit board, even to an electronic component having an electrode formed in high-density and in a zigzag arrangement pattern, which comprises an area overlapping an electrode.

Abstract translation: 用于安装的布线电路板的带状导体2的至少一部分，其中带状导体暴露以形成条纹图案，使得单独的导体可以连接到电子部件的电极E，被焊料覆盖 抗拒3。 具体部分是具有长端的带状导体的纵向方向上的一个部分，该部分包括与电极连接的区域，该电极连接到短端并沿条带宽度方向平行转移直到条带上的位置 导体长端。 结果，即使是具有以高密度和锯齿形排列图案形成的电极的电子部件，也可以向布线电路板提供能够抑制电极和布线图案之间的短路的结构，其包括 与电极重叠的区域。

公开(公告)号：US20060118457A1

公开(公告)日：2006-06-08

申请号：US10534190

申请日：2003-10-09

Applicant: Shuichi Kawasaki

Inventor： Shuichi Kawasaki

IPC: B65D85/00

CPC classification number: H01L23/49572 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/0097 ,  H05K3/3452 ,  H05K2201/0394 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2203/1545 ,  H01L2924/00

Abstract: A film carrier tape for mounting an electronic part includes a film carrier tape comprising an enlongated insulating film having a plurality of wiring patterns formed on a surface of the insulating film, the wiring patterns being made of a conductive metal, wherein the wiring patterns are each independently covered with a solder resist layer except a connecting terminal portion, and the solder resist layer formed on each surface of the wiring patterns is divided into plural sections. Warpage distortion that heretofore occurs on each of a plural film carriers arranged, such as CSP, COF and BGA, provided in a film carrier tape for mounting an electronic part in the width direction of the tape can be reduced.

Abstract translation: 用于安装电子部件的胶片载带包括胶片载体带，其包括具有形成在绝缘膜的表面上的多个布线图案的扩展的绝缘膜，所述布线图案由导电金属制成，其中布线图案各自 独立地覆盖除了连接端子部分之外的阻焊层，并且形成在布线图案的每个表面上的阻焊剂层被分成多个部分。 可以减少设置在用于在带的宽度方向上安装电子部件的胶片载带中布置的诸如CSP，COF和BGA之类的多个胶片载体上的翘曲变形。

公开(公告)号：US20060110919A1

公开(公告)日：2006-05-25

申请号：US11260748

申请日：2005-10-27

Applicant: Katsuyuki Moriya ,  Toshimitsu Hirai

Inventor： Katsuyuki Moriya ,  Toshimitsu Hirai

IPC: H01L21/44

CPC classification number: H01L51/0022 ,  H01L21/288 ,  H01L21/76838 ,  H01L27/3276 ,  H05K3/125 ,  H05K3/1258 ,  H05K2201/09909 ,  H05K2203/013

Abstract: A method of forming a wiring pattern in a predetermined area on a substrate using a droplet ejection process, including the steps of (a) forming a recess section for disposing a functional fluid in the predetermined area so that the predetermined area has a first region, a second region connected to the first region, and the third region connected to the second region, the second region having a narrower width than the first region and the third region, (b) ejecting to the first region the functional fluid containing a material for the wiring pattern, (c) drying the functional fluid ejected to the first region to form a film, (d) ejecting the functional fluid to the third region, and (e) drying the functional fluid ejected to the third region to form a film.

Abstract translation: 一种使用液滴喷射处理在基板上的预定区域中形成布线图案的方法，包括以下步骤：（a）形成用于在预定区域中布置功能流体的凹部，使得预定区域具有第一区域， 连接到第一区域的第二区域和连接到第二区域的第三区域，第二区域具有比第一区域和第三区域窄的宽度，（b）向第一区域喷射含有用于 布线图案，（c）将喷射到第一区域的功能流体干燥以形成膜，（d）将功能流体喷射到第三区域，以及（e）将排出到第三区域的功能流体干燥以形成膜 。

公开(公告)号：US20060110545A1

公开(公告)日：2006-05-25

申请号：US11256605

申请日：2005-10-21

Applicant: Naoyuki Toyoda

Inventor： Naoyuki Toyoda

IPC: G21H5/00 ,  B05D3/00 ,  C08J7/18 ,  B32B3/10

CPC classification number: H01L51/0022 ,  H01L21/288 ,  H01L21/76838 ,  H01L27/1292 ,  H01L27/3295 ,  H01L2924/0002 ,  H05K3/125 ,  H05K3/1258 ,  H05K2201/09909 ,  H05K2203/013 ,  H05K2203/0568 ,  H05K2203/1173 ,  Y10T428/24273 ,  H01L2924/00

Abstract: A method of forming a conductive pattern includes a step of forming a bank on a substrate and a step of applying a lyophobic agent to a part or whole of an upper face of the bank.

Abstract translation: 形成导电图案的方法包括在基板上形成堤的步骤以及将疏液剂施加到堤的上表面的一部分或全部的步骤。

公开(公告)号：US20060091526A1

公开(公告)日：2006-05-04

申请号：US11302144

申请日：2005-12-14

Applicant: Shinji Moriyama ,  Tomio Yamada

Inventor： Shinji Moriyama ,  Tomio Yamada

IPC: H01L23/12

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03G3/3042 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/183 ,  H05K3/3405 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10371 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

公开(公告)号：US07009117B2

公开(公告)日：2006-03-07

申请号：US10618593

申请日：2003-07-15

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/306 ,  H05K3/3447 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10651 ,  H05K2201/2036 ,  H05K2203/1178

Abstract: A printed circuit board, which is guaranteed to be free of defective soldering in mounting and connecting electric or electronic parts or devices to the printed circuit, has a circuit pattern printed on its substrate, and an anti-soldering layer is laid on the circuit pattern to prevent soldering material from sticking to the circuit pattern and silk-screen printing areas are laid on the anti-soldering layer to indicate where selected electric or electronic parts or devices are to be mounted. Each silk-screen printing area has terminal holes made therein. The board has a substrate-exposed zone traversing the silk-screen printing area to leave its opposite extensions open to the surrounding atmosphere, thereby allowing heated air and gases to escape from the interspace between the bottom of the electric or electronic part or device and the exposed substrate.

Abstract translation: 保证在电气或电子部件或设备安装和连接到印刷电路上无缺陷焊接的印刷电路板具有印刷在其基板上的电路图案，并且将抗焊层铺设在电路图案上 为了防止焊接材料粘附到电路图案上，并且丝网印刷区域铺设在防焊层上，以指示所选择的电气或电子部件或装置将要安装在哪里。 每个丝网印刷区域都具有端子孔。 该板具有穿过丝网印刷区域的基板暴露区域，以使其相对的延伸部向周围的大气开放，从而允许加热的空气和气体从电气或电子部件或装置的底部与 曝光底物。

公开(公告)号：US20060045963A1

公开(公告)日：2006-03-02

申请号：US11206802

申请日：2005-08-19

Applicant: Toshimitsu Hirai ,  Shinri Sakai

Inventor： Toshimitsu Hirai ,  Shinri Sakai

IPC: C23C26/00 ,  C23C30/00

CPC classification number: H01L51/0022 ,  C23C24/00 ,  H01L51/055 ,  H05K3/125 ,  H05K2201/09727 ,  H05K2201/09909 ,  H05K2203/013

Abstract: The invention provides a method of forming a wiring pattern in which a conductive material layer is formed in a pattern formation region having a first region, which is bordered by a bank pattern and has a first width, and a second region, which touches the first region and has a second width smaller than the first width, on a substrate, by discharging a droplet of a conductive material in a liquid phase using a droplet discharge device. The method includes forming the conductive material layer to cover the first region and the second region, by discharging the droplet having a diameter smaller than the first width and greater than the second width toward the first region. In this case, the droplet is discharged such that the droplet lands at a position that faces a boundary line between the first region and the second region.

Abstract translation: 本发明提供一种形成布线图案的方法，其中在具有第一区域的图案形成区域中形成导电材料层，所述第一区域由堤形图案界定并具有第一宽度，第二区域与第一区域接触， 并且在基板上通过使用液滴喷射装置以液相排出导电材料的液滴而具有小于第一宽度的第二宽度。 该方法包括通过将具有小于第一宽度的直径小于第二宽度的墨滴排出第一区域，形成覆盖第一区域和第二区域的导电材料层。 在这种情况下，液滴被排出，使得液滴在面对第一区域和第二区域之间的边界线的位置处着落。

公开(公告)号：US06966482B2

公开(公告)日：2005-11-22

申请号：US10340798

申请日：2003-01-13

Applicant: Makoto Totani ,  Toshihiro Miyake ,  Tomohiro Yokochi ,  Takehito Teramae ,  Yoshitaro Yazaki ,  Kazuyuki Deguchi ,  Hajime Nakagawa

Inventor： Makoto Totani ,  Toshihiro Miyake ,  Tomohiro Yokochi ,  Takehito Teramae ,  Yoshitaro Yazaki ,  Kazuyuki Deguchi ,  Hajime Nakagawa

IPC: H01R12/62 ,  H05K3/34 ,  H05K3/36 ,  H05K1/03 ,  B23K31/02 ,  H01L23/48

CPC classification number: H05K3/363 ,  H05K3/3452 ,  H05K3/3494 ,  H05K2201/0129 ,  H05K2201/091 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10772 ,  H05K2203/0195 ,  H05K2203/0278 ,  H05K2203/065

Abstract: Lands formed on a flexible printed circuit board are electrically connected with lands formed on a rigid printed circuit board through solder. At this point, solder resist is formed between neighboring two lands on the rigid printed circuit board, and is terminated with an end portion that is interposed between the rigid printed circuit board and the flexible printed circuit board. Accordingly, even when surplus solder is extruded onto the rigid printed circuit board, the solder resist can prevent solder bridges from being formed between the lands.

Abstract translation: 形成在柔性印刷电路板上的焊盘通过焊料与刚性印刷电路板上形成的焊盘电连接。 此时，在刚性印刷电路板上的相邻的两个焊盘之间形成阻焊剂，并且端接有刚性印刷电路板和柔性印刷电路板之间的端部。 因此，即使剩余焊料被挤出到刚性印刷电路板上，阻焊剂也可以防止在焊盘之间形成焊料桥。